| Variable delay circuit for delaying input data H Kawai, M Yoshimoto US Patent 4,953,128, 1990 | 164 | 1990 |
| Layout designing method for a semiconductor integrated circuit device S Nakagawa, H Kawai US Patent 5,365,454, 1994 | 110 | 1994 |
| A 250-MHz 18-Mb full ternary CAM with low-voltage matchline sensing scheme in 65-nm CMOS I Hayashi, T Amano, N Watanabe, Y Yano, Y Kuroda, M Shirata, K Dosaka, ... IEEE journal of solid-state circuits 48 (11), 2671-2680, 2013 | 77 | 2013 |
| 3D graphics LSI core for mobile phone" Z3D". M Kameyama, Y Kato, H Fujimoto, H Negishi, Y Kodama, Y Inoue, ... Graphics Hardware 2003, 60-67, 2003 | 66 | 2003 |
| Semiconductor integrated circuit for processing image data H Kawai, Y Inoue, H Nakamura US Patent 5,673,422, 1997 | 46 | 1997 |
| Direct memory access control device and method in a multiprocessor system accessing local and shared memory H Kawai, H Terane US Patent 5,584,010, 1996 | 45 | 1996 |
| Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel H Kawai, R Streitenberger, Y Inoue, K Yoshimatsu, J Kobara, H Negishi US Patent 6,603,481, 2003 | 33 | 2003 |
| Square root extraction circuit and floating-point square root extraction device H Kawai, R Streitenberger, Y Inoue, H Morinaka US Patent 6,820,107, 2004 | 32 | 2004 |
| PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device R Streitenberger, H Kawai US Patent 6,272,582, 2001 | 28 | 2001 |
| Vehicle S Sasaki, M Fujii, S Shibasaki, N Hakamata, S Yano US Patent 10,293,684, 2019 | 27* | 2019 |
| A chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST H Fujiwara, M Yabuuchi, H Nakano, H Kawai, K Nii, K Arimoto 2011 Symposium on VLSI circuits-digest of technical papers, 76-77, 2011 | 27 | 2011 |
| Normally-off MCU architecture for low-power sensor node M Hayashikoshi, Y Sato, H Ueki, H Kawai, T Shimizu 2014 19th Asia and South Pacific design automation conference (ASP-DAC), 12-16, 2014 | 26 | 2014 |
| Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency H Kawai, S Nakagawa US Patent 4,877,974, 1989 | 26 | 1989 |
| Program control operation to execute a loop processing not immediately following a loop instruction R Streitenberger, H Kawai, Y Inoue US Patent 5,657,485, 1997 | 23 | 1997 |
| Bridge device for connecting multiple devices to one slot R Streitenberger, H Kawai, Y Inoue, J Kobara US Patent 6,675,251, 2004 | 21 | 2004 |
| A 10 Mb frame buffer memory with Z-compare and A-blend units K Inoue, H Nakamura, H Kawai IEEE Journal of Solid-State Circuits 30 (12), 1563-1568, 1995 | 20 | 1995 |
| Image processing LSI circuit with image preprocessing, feature extraction and matching H Kawai, Y Inoue, R Streitenberger US Patent 5,715,436, 1998 | 16 | 1998 |
| SIMD processor operating with a plurality of parallel processing elements in synchronization Y Inoue, H Kawai, R Streitenberger US Patent 5,729,758, 1998 | 15 | 1998 |
| Design automation system for analog circuits based on fuzzy logic M Hashizume, HY Kawai, K Nii, T Tamesada 1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 4.6/1-4.6/4, 1989 | 15 | 1989 |
| Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports R Streitenberger, H Kawai, Y Inoue, J Kobara US Patent 7,054,979, 2006 | 14 | 2006 |
