| Scarab: A single cycle adaptive routing and bufferless network M Hayenga, NE Jerger, M Lipasti 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009 | 188 | 2009 |
| Sources of error in full-system simulation A Gutierrez, J Pusdesris, RG Dreslinski, T Mudge, C Sudanthi, ... 2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014 | 135 | 2014 |
| Memory management BC Bare, SK Wakumoto US Patent 9,311,227, 2016 | 29* | 2016 |
| The nox router M Hayenga, M Lipasti Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 29 | 2011 |
| Revolver: Processor architecture for power efficient loop execution M Hayenga, VRK Naresh, MH Lipasti 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 21 | 2014 |
| NR1H4 nuclear receptor binding compounds U Bauer, Z Cheruvallath, U Deuschle, E Dneprovskaia, T Gahman, ... US Patent 6,974,830, 2005 | 20 | 2005 |
| Pitfalls of ORION-Based Simulation M Hayenga, DR Johnson, M Lipasti Workshop on Duplicating, Deconstructing, and Debunking 35, 6, 2012 | 17 | 2012 |
| Indexing entries of a storage structure shared between multiple threads MB Hayenga, CG Dunham, D Sunwoo US Patent 10,185,731, 2019 | 16 | 2019 |
| Accurate system-level performance modeling and workload characterization for mobile internet devices M Hayenga, C Sudanthi, M Ghosh, P Ramrakhyani, N Paver Proceedings of the 9th workshop on MEmory performance: DEaling with …, 2008 | 11 | 2008 |
| MadCache: A PC-aware cache insertion policy M Hayenga, A Nere, M Lipasti JWAC 2010-1st JILP Worshop on Computer Architecture Competitions: cache …, 2010 | 8 | 2010 |
| Power-Efficient Loop Execution Techniques MB Hayenga The University of Wisconsin-Madison, 2013 | 1 | 2013 |
| Indexing entries of a storage structure shared between multiple threads MB Hayenga, CG Dunham, D Sunwoo US Patent 10,725,992, 2020 | | 2020 |
| Memory dependence prediction CG Dunham, MB Hayenga US Patent 10,324,727, 2019 | | 2019 |
| Prefetching using a prefetch lookup table identifying previously accessed cache lines MB Hayenga, CD Emmons US Patent 9,582,282, 2017 | | 2017 |
| Dally, William J., 83, 465 de Kruijf, Marc, 140 Diamos, Gregory, 477 Ding, Wei, 489 Drake, Alan J. TM Aamodt, AH Abdel-Gawad, AR Adl-Tabatabai, J Ahn, K Aisopos, ... | | |
Mikko LipastiProfessor, Electrical and Computer Engineering, University of Wisconsin-MadisonVerified email at engr.wisc.edu
