| High performance bulk planar 20nm CMOS technology for low power mobile applications H Shang, S Jain, E Josse, E Alptekin, MH Nam, SW Kim, KH Cho, I Kim, ... 2012 Symposium on VLSI Technology (VLSIT), 129-130, 2012 | 30 | 2012 |
| Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme RP Srivastava, E Huang US Patent 8,114,769, 2012 | 24 | 2012 |
| Methods of fabricating BEOL interlayer structures SK Singh, RP Srivastava, TJ Tang, MA Zaleski US Patent 9,362,162, 2016 | 14 | 2016 |
| Method to reduce depth delta between dense and wide features in dual damascene structures RP Srivastava, OO Ogunsola, C Child, MSKV Pallachalil, H Hichri, ... US Patent 8,822,342, 2014 | 13 | 2014 |
| Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same SK Singh, RP Srivastava, X Wu, A Sehgal, TJ Tang US Patent 9,576,894, 2017 | 11 | 2017 |
| Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first scheme RP Srivastava, H Wendt, KA Kumar US Patent App. 11/863,746, 2009 | 10 | 2009 |
| Methods and structures for back end of line integration SK Singh, RP Srivastava, MA Zaleski, A Sehgal US Patent 9,117,822, 2015 | 9 | 2015 |
| Air gap formation in back-end-of-line structures RP Srivastava, SK Singh US Patent App. 15/882,465, 2019 | 7 | 2019 |
| Methods of patterning insulating layers using etching techniques that compensate for etch rate variations W Park, KA Kumar, JE Linville, AD Lisi, RP Srivastava, HW Wendt US Patent 8,058,176, 2011 | 7 | 2011 |
| Lithographic patterning to form fine pitch features SK Singh, SS Mehta, S Singh, RP Srivastava US Patent 10,504,774, 2019 | 6 | 2019 |
| Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks X Wang, SHU Jiehui, B O'brien, TA Spooner, J Liu, RP Srivastava US Patent 10,192,780, 2019 | 6 | 2019 |
| Interconnect formation process using wire trench etch prior to via etch, and related interconnect Singh, S Sunil K. (Mechanicville, NY), G Ravi P. (Clifton Park, NY), ... http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u …, 2019 | 5 | 2019 |
| Interconnect structure with method of forming the same RP Srivastava, SK Singh US Patent App. 15/867,894, 2019 | 5 | 2019 |
| Interconnect structure with method of forming the same Srivastava, S Ravi P. (Clifton Park, NY), NY Sunil K. (Mechanicville US Patent 10,312,188, 2019 | 5 | 2019 |
| Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques S Mehta, TQ Chen, V Chauhan, R Srivastava, C Labelle, M Kelling US Patent 8,932,961, 2015 | 5 | 2015 |
| Competitive and cost effective copper/low-k interconnect (BEOL) for 28 nm CMOS technologies R Augur, C Child, JH Ahn, TJ Tang, L Clevenger, D Kioussis, H Masuda, ... Microelectronic engineering 92, 42-44, 2012 | 5 | 2012 |
| Plasma etch challenges for porous low-k materials for 32nm and beyond C Labelle, R Srivastava, Y Yin, TQ Chen, R Koshy, Y Mignot, J Arnold, ... Advanced Etch Technology for Nanopatterning 8328, 58-64, 2012 | 5 | 2012 |
| Trench etch: Optimization with 193 nm resist LCH SIEW, YONG KONG, Raymond JOY, Dennis TAN, WUPING LIU, Ravi SRIVASTAVA ... Semiconductor international 26 (9), 62-62, 2003 | 5 | 2003 |
| Methods and devices for back end of line via formation SK Singh, SS Mehta, RP Srivastava US Patent 9,691,654, 2017 | 4 | 2017 |
| Integrated circuit system with ultra-low k dielectric and method of manufacture thereof RP Srivastava US Patent 8,420,947, 2013 | 4 | 2013 |
Sunil Kumar SinghSamsung, HFC, GlobalFoundries, TSMC, Indian Institute of Technology Bombay, Indian Institute ofVerified email at samsung.com
