| Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ... Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 545 | 2016 |
| Scalpel: Customizing dnn pruning to the underlying hardware parallelism J Yu, A Lukefahr, D Palframan, G Dasika, R Das, S Mahlke ACM SIGARCH Computer Architecture News 45 (2), 548-560, 2017 | 353 | 2017 |
| A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw IEEE Journal of Solid-State Circuits 46 (1), 18-31, 2010 | 189 | 2010 |
| Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction YP Raykov, E Ozer, G Dasika, A Boukouvalas, MA Little Proceedings of the 2016 ACM international joint conference on pervasive and …, 2016 | 110 | 2016 |
| Bridging the computation gap between programmable processors and hardwired accelerators K Fan, M Kudlur, G Dasika, S Mahlke 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 97 | 2009 |
| APOGEE: Adaptive prefetching on GPUs for energy efficiency A Sethia, G Dasika, M Samadi, S Mahlke Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 81 | 2013 |
| A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation D Bull, S Das, K Shivshankar, G Dasika, K Flautner, D Blaauw 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 284-285, 2010 | 68 | 2010 |
| Compiler managed dynamic instruction placement in a low-power code cache RA Ravindran, PD Nagarkar, GS Dasika, ED Marsman, RM Senger, ... International Symposium on Code Generation and Optimization, 179-190, 2005 | 68 | 2005 |
| Partitioning variables across register windows to reduce spill code in a low-power processor RA Ravindran, RM Senger, ED Marsman, GS Dasika, MR Guthaus, ... IEEE Transactions on Computers 54 (8), 998-1012, 2005 | 36 | 2005 |
| BONSEYES: platform for open development of systems of artificial intelligence T Llewellynn, MM Fernández-Carrobles, O Deniz, S Fricker, A Storkey, ... Proceedings of the computing frontiers conference, 299-304, 2017 | 32 | 2017 |
| Compressing rnns for iot devices by 15-38x using kronecker products U Thakker, J Beu, D Gope, C Zhou, I Fedorov, G Dasika, M Mattina arXiv preprint arXiv:1906.02876, 2019 | 31 | 2019 |
| Efficient winograd or cook-toom convolution kernel implementation on widely used mobile cpus P Maji, A Mundy, G Dasika, J Beu, M Mattina, R Mullins 2019 2nd Workshop on Energy Efficient Machine Learning and Cognitive …, 2019 | 27 | 2019 |
| PEPSC: A power-efficient processor for scientific computing G Dasika, A Sethia, T Mudge, S Mahlke 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 27 | 2011 |
| A 16-bit low-power microcontroller with monolithic MEMS-LC clocking ED Marsman, RM Senger, MS McCorquodale, MR Guthaus, ... 2005 IEEE International Symposium on Circuits and Systems, 624-627, 2005 | 26 | 2005 |
| Increasing the number of effective registers in a low-power processor using a windowed register file RA Ravindran, RM Senger, ED Marsman, GS Dasika, MR Guthaus, ... Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 26 | 2003 |
| Run-time efficient RNN compression for inference on edge devices U Thakker, J Beu, D Gope, G Dasika, M Mattina 2019 2nd Workshop on Energy Efficient Machine Learning and Cognitive …, 2019 | 21 | 2019 |
| Ternary hybrid neural-tree networks for highly constrained iot applications D Gope, G Dasika, M Mattina Proceedings of Machine Learning and Systems 1, 190-200, 2019 | 20 | 2019 |
| Mighty-morphing power-SIMD G Dasika, M Woh, S Seo, N Clark, T Mudge, S Mahlke Proceedings of the 2010 international conference on Compilers, architectures …, 2010 | 20 | 2010 |
| Estimating a number of occupants in a region YP Raykov, E Özer, GS Dasika US Patent 10,607,147, 2020 | 19 | 2020 |
| DVFS in loop accelerators using BLADES G Dasika, S Das, K Fan, S Mahlke, D Bull Proceedings of the 45th annual Design Automation Conference, 894-897, 2008 | 19 | 2008 |
