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R Sai Chandra Teja
R Sai Chandra Teja
Co-Founder: Green PMU Semi, Independent Researcher
Verified email at alumni.iith.ac.in
Title
Cited by
Cited by
Year
A low-voltage design of controller-based ADPLL for implantable biomedical devices
J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka
2015 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2015
102015
Design and emulation of all-digital phase-locked loop on FPGA
S Radhapuram, T Yoshihara, T Matsuoka
Electronics 8 (11), 1307, 2019
82019
A subthreshold low-voltage low-phase-noise CMOS LC-VCO with resistive biasing
J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka
Circuits and Systems 6 (5), 136-142, 2015
82015
A low-power CMOS programmable frequency divider with novel retiming scheme
S Radhapuram, J Bae, I Jo, T Kihara, T Matsuoka
IEICE Electronics Express, 12.20141233, 2015
72015
A design of 0.7-V 400-MHz digitally-controlled oscillator
J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka
IEICE Transactions on Electronics 98 (12), 1179-1186, 2015
62015
A design of 0.7-V 400-MHz all-digital phase-locked loop for implantable biomedical devices
J Bae, S Radhapuram, I Jo, W Wang, T Kihara, T Matsuoka
IEICE Transactions on Electronics 99 (4), 431-439, 2016
52016
A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology
J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka
2015 IEEE International Symposium on Radio-Frequency Integration Technology …, 2015
42015
Analysis of a controller-based all-digital phase-locked loop
S Radhapuram, J Bae, I Jo, W Wang, T Matsuoka
Far East Journal of Electronics and Communications 15 (1), 57-73, 2015
42015
ERRATUM: ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP
S Radhapuram, J Bae, I Jo, W Wang, T Matsuoka
Far East Journal of Electronics and Communications 16 (1), 199-201, 2016
32016
WaferSegClassNet-A light-weight network for classification and segmentation of semiconductor wafer defects
S Nag, D Makwana, SC Teja R, S Mittal, C Krishna Mohan
Computers in Industry 142, 103720, 2022
22022
ClarifyNet: A high-pass and low-pass filtering based CNN for single image dehazing
O Susladkar, G Deshmukh, S Nag, A Mantravadi, D Makwana, ...
Journal of Systems Architecture 132, 102736, 2022
12022
Inferring DNN layer-types through a Hardware Performance Counters based Side Channel Attack
BAD Kumar, SC Teja R, S Mittal, B Panda, CK Mohan
The First International Conference on AI-ML-Systems, 1-7, 2021
12021
TPFNet: A Novel Text In-painting Transformer for Text Removal
O Susladkar, D Makwana, G Deshmukh, S Mittal, R Singhal
arXiv preprint arXiv:2210.14461, 2022
2022
FEEDNet: a feature enhanced encoder-decoder LSTM network for nuclei instance segmentation for histopathological diagnosis
G Deshmukh, O Susladkar, D Makwana, S Mittal
Physics in Medicine & Biology 67 (19), 195011, 2022
2022
ACLNet: an attention and clustering-based cloud segmentation network
D Makwana, S Nag, O Susladkar, G Deshmukh, SC Teja R, S Mittal, ...
Remote Sensing Letters 13 (9), 865-875, 2022
2022
Involution Receptive Field Network for COVID-19 Diagnosis
M Dhruv, RSC Teja, RS Devi, SN Kumar
New Trends in Physical Science Research Vol. 6, 29-37, 2022
2022
InRFNet: Involution Receptive Field Network for COVID-19 Diagnosis
M Dhruv, RSC Teja, RS Devi, SN Kumar
Journal of Physics: Conference Series 2161 (1), 012064, 2022
2022
Memory system and control method thereof
SCT Radhapuram, M Takada
US Patent App. 17/010,002, 2021
2021
Memory system and control method
サイ チャンヅラ テジャ ラデャプラム万里江 高田
JP Patent JP2,021,149,421 A, 2021
2021
Study on Behavior-Level Modeling and Top-Down Approach Design of All-Digital Phase-Locked Loop
SCT Radhapuram
2020
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