Zissis Poulos
Zissis Poulos
Verified email at eecg.toronto.edu
Cited by
Cited by
Astraea: A decentralized blockchain oracle
J Adler, R Berryhill, A Veneris, Z Poulos, N Veira, A Kastania
2018 IEEE international conference on internet of things (IThings) and IEEE …, 2018
Laconic deep learning inference acceleration
S Sharify, AD Lascorz, M Mahmoud, M Nikolic, K Siu, DM Stuart, Z Poulos, ...
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019
Bit-tactical: A software/hardware approach to exploiting value and bit sparsity in neural networks
A Delmas Lascorz, P Judd, DM Stuart, Z Poulos, M Mahmoud, S Sharify, ...
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
Bit-tactical: Exploiting ineffectual computations in convolutional neural networks: Which, why, and how
A Delmas, P Judd, DM Stuart, Z Poulos, M Mahmoud, S Sharify, M Nikolic, ...
arXiv preprint arXiv:1803.03688, 2018
Clustering-based failure triage for rtl regression debugging
Z Poulos, A Veneris
2014 International Test Conference, 1-10, 2014
Shapeshifter: Enabling fine-grain data width adaptation in deep learning
AD Lascorz, S Sharify, I Edo, DM Stuart, OM Awad, P Judd, M Mahmoud, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Deep hedging of derivatives using reinforcement learning
J Cao, J Chen, J Hull, Z Poulos
The Journal of Financial Data Science 3 (1), 10-27, 2021
Leveraging reconfigurability to raise productivity in FPGA functional debug
Z Poulos, YS Yang, J Anderson, A Veneris, B Le
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 292-295, 2012
Clustering-based revision debug in regression verification
D Maksimovic, A Veneris, Z Poulos
2015 33rd IEEE International Conference on Computer Design (ICCD), 32-37, 2015
Simulation and satisfiability guided counter-example triage for rtl design debugging
Z Poulos, YS Yang, A Veneris, B Le
Fifteenth International Symposium on Quality Electronic Design, 618-624, 2014
Exploiting Typical Values to Accelerate Deep Learning
A Moshovos, J Albericio, P Judd, AD Lascorz, S Sharify, Z Poulos, ...
Computer 51 (5), 18-30, 2018
Exemplar-based failure triage for regression design debugging
Z Poulos, A Veneris
Journal of Electronic Testing 32 (2), 125-136, 2016
Failure triage in RTL regression verification
Z Poulos, A Veneris
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
A failure triage engine based on error trace signature extraction
Z Poulos, YS Yang, A Veneris
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 73-78, 2013
Suspect set prediction in RTL bug hunting
N Veira, Z Poulos, A Veneris
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Accelerating post silicon debug of deep electrical faults
B Le, D Sengupta, A Veneris, Z Poulos
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 61-66, 2013
Fast GPU-based influence maximization within finite deadlines via node-level parallelism
K Pal, Z Poulos, E Kim, A Veneris
Industrial Conference on Data Mining, 151-165, 2017
Learning lemma support graphs in quip and IC3
R Berryhill, N Veira, A Veneris, Z Poulos
2017 IEEE 2nd International Verification and Security Workshop (IVSW), 105-110, 2017
Variational autoencoders: A hands-off approach to volatility
M Bergeron, N Fung, Z Poulos, JC Hull, A Veneris
Available at SSRN 3827447, 2021
On public crowdsource-based mechanisms for a decentralized blockchain oracle
K Nelaturu, J Adler, M Merlini, R Berryhill, N Veira, Z Poulos, A Veneris
IEEE Transactions on Engineering Management 67 (4), 1444-1458, 2020
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