| Micro-pages: increasing DRAM efficiency with locality-aware data placement K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ... ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010 | 309 | 2010 |
| Efficient scrub mechanisms for error-prone emerging memories M Awasthi, M Shevgoor, K Sudan, B Rajendran, R Balasubramonian, ... IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 284* | 2012 |
| USIMM: the Utah SImulated Memory Module N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ... | 201 | 2012 |
| Handling the problems and opportunities posed by multiple on-chip memory controllers M Awasthi, DW Nellans, K Sudan, R Balasubramonian, A Davis Proceedings of the 19th international conference on Parallel architectures …, 2010 | 177 | 2010 |
| Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall K Sudan, K Rajamani, W Huang, JB Carter IEEE Transactions on Computers, 2012 | 25 | 2012 |
| NAND-Flash: Fast Storage or Slow Memory? K Sudan, A Badam, D Nellans Non-Volatile Memory Workshop (NVMW), 2012 | 24 | 2012 |
| Usimm: the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ... Utah and Intel Corp, 2012 | 23 | 2012 |
| Increasing memory capacity in power-constrained systems JB Carter, W Huang, K Rajamani, FL Rawson III, K Sudan US Patent 8,738,875, 2014 | 22 | 2014 |
| Cache with compressed data and tag A Saidi, K Sudan, AJ Rushing, A Hansson, M Filippo US Patent 9,996,471, 2018 | 16 | 2018 |
| Handling PCM resistance drift with device, circuit, architecture, and system solutions M Awasthi, M Shevgoor, K Sudan, R Balasubramonian, B Rajendran, ... Non-Volatile Memories Workshop, 2011 | 16 | 2011 |
| A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O K Sudan, S Balakrishnan, S Lie, M Xu, D Mallick, G Lauterbach, ... 15th International Symposium on High-Performance Computer Architecture (HPCA-15), 2013 | 15 | 2013 |
| Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service K Sudan, S Srinivasan, R Balasubramonian, R Iyer International Conference on Parallel Architectures and Compilation …, 2012 | 15 | 2012 |
| Method and apparatus for hardware management of multiple memory pools A Pellegrini, K Sudan, A Saidi, WA Elsasser US Patent 10,417,141, 2019 | 14 | 2019 |
| Improving server performance on multi-cores via selective off-loading of os functionality D Nellans, K Sudan, E Brunvand, R Balasubramonian Computer Architecture: ISCA 2010 International Workshops A4MMC, AMAS-BT …, 2012 | 14 | 2012 |
| Managing data placement in memory systems with multiple memory controllers M Awasthi, D Nellans, K Sudan, R Balasubramonian, A Davis International Journal of Parallel Programming 40, 57-83, 2012 | 11 | 2012 |
| Data placement for efficient main memory access K Sudan the University of Utah, 2013 | 9 | 2013 |
| Increasing memory capacity in power-constrained systems JB Carter, W Huang, K Rajamani, FL Rawson III, K Sudan US Patent 8,719,527, 2014 | 3 | 2014 |
| Understanding the behavior of Pthread applications on non-uniform cache architectures GS Sachdev, K Sudan, MW Hall, R Balasubramonian 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 2 | 2011 |
| Hardware prediction of OS run-length for fine-grained resource customization D Nellans, K Sudan, R Balasubramonian, E Brunvand 2010 IEEE International Symposium on Performance Analysis of Systems …, 2010 | 1 | 2010 |
| A Parallel Algorithm for Discrete Gabor Transforms. K Sudan, N Saggar, A De PDPTA, 228-231, 2007 | 1 | 2007 |
Rajeev BalasubramonianProfessor, School of Computing, University of UtahVerified email at cs.utah.edu
