Xuechao Wei
Title
Cited by
Cited by
Year
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
2342017
TGPA: tile-grained pipeline architecture for low latency CNN inference
X Wei, Y Liang, X Li, CH Yu, P Zhang, J Cong
Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018
282018
Overcoming data transfer bottlenecks in FPGA-based DNN accelerators via layer conscious memory management
X Wei, Y Liang, J Cong
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
222019
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems
X Wei, Y Liang, T Wang, S Lu, J Cong
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 488-493, 2017
192017
Frequency improvement of systolic array-based CNNs on FPGAs
J Zhang, W Zhang, G Luo, X Wei, Y Liang, J Cong
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019
152019
FlexBFS: a parallelism-aware implementation of breadth-first search on GPU
G Liu, H An, W Han, X Li, T Sun, W Zhou, X Wei, X Tang
Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of …, 2012
152012
FTDL: An FPGA-tailored Architecture for Deep Learning Systems.
R Shi, Y Ding, X Wei, H Liu, HKH So, C Ding
FPGA, 320, 2020
42020
Overcoming data transfer bottlenecks in dnn accelerators via layer-conscious memory managment
X Wei, Y Liang, P Zhang, CH Yu, J Cong
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
42019
Generating Systolic Array Accelerators With Reusable Blocks
L Jia, L Lu, X Wei, Y Liang
IEEE Micro 40 (4), 85-92, 2020
32020
FTDL: a tailored FPGA-overlay for deep learning with high scalability
R Shi, Y Ding, X Wei, H Li, H Liu, HKH So, C Ding
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
22020
Systems and methods for systolic array design from a high-level program
P Zhang, CH Yu, X Wei, P Pan
US Patent 10,838,910, 2020
12020
Distributed Control Independence for Composable Multi-processors
M Mao, H An, T Sun, Q Li, B Deng, X Wei, J Zhou
2012 IEEE/ACIS 11th International Conference on Computer and Information …, 2012
12012
Systems And Methods For Systolic Array Design From A High-Level Program
P Zhang, CH Yu, X Wei, P Pan
US Patent App. 17/096,742, 2021
2021
Framework to Accelerate Single-threaded Applications by Hyperblock Reformation on EDGE Architectures
XC Wei, H An, MJ Mao
Journal of Chinese Computer Systems 33 (10), 2249-2254, 2012
2012
Distributed replay protocol for distributed uniprocessors
M Mao, H An, B Deng, T Sun, X Wei, W Zhou, W Han
Proceedings of the 26th ACM international conference on Supercomputing, 3-14, 2012
2012
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