Ramin Rajaei, Ph.D.

Процитировано

	Все	Начиная с 2019 г.
Статистика цитирования	1182	906
h-индекс	23	20
i10-индекс	37	32

200

100

150

20122013201420152016201720182019202020212022202320244 6 12 21 60 70 96 107 171 165 174 181 104

Общий доступ

Просмотреть все

6 статей

5 статей

доступно

недоступно

На основе финансирования

Соавторы

Xiaobo Sharon HuUniversity of Notre Dame, Department of Computer Science and EngineeringПодтвержден адрес электронной почты в домене nd.edu
Michael NiemierUniversity of Notre DameПодтвержден адрес электронной почты в домене nd.edu
Mahdi FazeliAssociate Professor, School of Information Technology, Halmstad UniversityПодтвержден адрес электронной почты в домене hh.se
Kai NiUniversity of Notre DameПодтвержден адрес электронной почты в домене nd.edu
Mohammad Hossein MoaiyeriAssociate Professor of Electronics and Computer Engineering, Shahid Beheshti University, IranПодтвержден адрес электронной почты в домене sbu.ac.ir
Bahar AsgariAssistant Professor, University of Maryland, College Park, Department of Computer ScienceПодтвержден адрес электронной почты в домене umd.edu
Saeed Bagheri ShourakiProfessor of Electrical Engineering, Sharif UniversityПодтвержден адрес электронной почты в домене sharif.edu
Siamak MohammadiAssociate Professor of Electrical and Computer Eng., University of TehranПодтвержден адрес электронной почты в домене ut.ac.ir
Hamid Reza ShahdoostiAssociate Professor of Electrical Engineering, Hamedan University of TechnologyПодтвержден адрес электронной почты в домене hut.ac.ir
Iman KhajenasiriCochlear Implants , ASIC architectПодтвержден адрес электронной почты в домене esat.kuleuven.be
Bizhan RashidianProfessor of Electrical Engineering, Sharif University of TechnologyПодтвержден адрес электронной почты в домене sharif.ir
Yier JinAssociate Professor, University of FloridaПодтвержден адрес электронной почты в домене ece.ufl.edu
Pierre - Emmanuel GAILLARDONAssociate Professor, University of UtahПодтвержден адрес электронной почты в домене utah.edu
Shaahin HessabiDept. of Computer Science & Engineering, Sharif University of Technology, IranПодтвержден адрес электронной почты в домене sharif.edu
Sayeef SalahuddinTSMC Distinguished Professor of EECS, University of California, BerkeleyПодтвержден адрес электронной почты в домене berkeley.edu
Suman DattaJoseph M. Pettit Chair ProfessorПодтвержден адрес электронной почты в домене gatech.edu

Ramin Rajaei, Ph.D.

Senior FPGA Design Engineer at Jariet Technologies, Inc

Подтвержден адрес электронной почты в домене jariettech.com - Главная страница

FPGA Design Computer Architecture Machine/Deep Learning Fault Tolerance


Название По числу цитат По году По названию	Процитировано Процитировано	Год
Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies R Rajaei, B Asgari, M Tabandeh, M Fazeli IEEE Transactions on Device and Materials Reliability 15 (3), 429 - 436, 2015	91	2015
Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation R Rajaei, M Tabandeh, M Fazeli Microelectronics Reliability 53 (6), 912-924, 2013	69	2013
Fully Nonvolatile and Low Power Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction with Spin-Hall Effect Assistance A Amirany, R Rajaei IEEE Transactions on Magnetics, 2018	59	2018
Radiation Hardened Design of Nonvolatile MRAM-based FPGA R Rajaei IEEE Transactions on Magnetics (TMAG), 2016	58	2016
Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations R Rajaei, M Tabandeh, M Fazeli Journal of Circuits, Systems and Computers 24 (01), 1550007, 2015	57	2015
A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic F Razi, MH Moaiyeri, R Rajaei, S Mohammadi IEEE Transactions on Nanotechnology, 2019	52	2019
Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design R Rajaei, S Bakhtavari Mamaghani IEEE Transactions on Device and Materials Reliability (TDMR), 2017	47	2017
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories A Kazemi, MM Sharifi, AF Laguna, F Müller, R Rajaei, R Olivo, T Kämpfe, ... Design, Automation and Test in Europe Conference (DATE'21), 2021	43	2021
A novel hybrid algorithm for creating self-organizing fuzzy neural networks O Khayat, MM Ebadzadeh, HR Shahdoosti, R Rajaei, I Khajehnasiri Neurocomputing 73 (1-3), 517-524, 2009	40	2009
In-memory computing with associative memories: A cross-layer perspective XS Hu, M Niemier, A Kazemi, AF Laguna, K Ni, R Rajaei, MM Sharifi, ... 2021 IEEE International Electron Devices Meeting (IEDM), 25.2. 1-25.2. 4, 2021	39	2021
Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing A Amirany, R Rajaei SPIN, 2019	38	2019
Single event upset immune latch circuit design using C-element R Rajaei, M Tabandeh, B Rashidian 2011 9th IEEE International Conference on ASIC, 252-255, 2011	35	2011
Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop A Amirany, F Marvi, K Jafari, R Rajaei IEEE Transactions on Nanotechnology, 2019	34	2019
Nonvolatile Low-Cost Approximate Spintronic Full-Adders for Computing-in-Memory Architectures R Rajaei, A Amirany IEEE Transactions on Magnetics, 2020	32	2020
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology R Rajaei, B Asgari, M Tabandeh, M Fazeli Turkish Journal of Electrical Engineering & Computer Sciences, 2016	32	2016
Compact Single-Phase-Search Multi-State Content Addressable Memory Design using 1 FeFET/Cell R Rajaei, MM Sharifi, A Kazemi, M Niemier, XS Hu IEEE Transaction on Electron Devices, 2021	31	2021
Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics R Rajaei, M Fazeli, M Tabandeh IEEE Transactions on Magnetics (TMAG) 51 (6), 2014	30	2014
A Low-Cost and Highly Reliable Spintronics True Random Number Generator Circuit for Secure Cryptography I Alibeigi, A Amirany, R Rajaei, M Tabandeh, S Bagheri Shouraki SPIN, 2019	28	2019
Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits R Rajaei Microelectronics Reliability (MR), 2017	27	2017
Low Power, Reliable, and Nonvolatile MSRAM Cell for Facilitating Power Gating and Nonvolatile Dynamically Reconfiguration R Rajaei, A Gholipour IEEE Transactions on Nanotechnology, 2018	25	2018

В данный момент система не может выполнить эту операцию. Повторите попытку позднее.

Статьи 1–20

Ссылок за год

Повторяющиеся цитирования

Объединенные цитирования

СоавторыСоавторы

Подписаться

Процитировано

Соавторы