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Aniruddha Vaidya
Aniruddha Vaidya
GPU Compute Architect, Nvidia Corporation
Verified email at nvidia.com
Title
Cited by
Cited by
Year
A class of hypercube-like networks
AS Vaidya, PSN Rao, SR Shankar
Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed …, 1993
1431993
Integration Challenges and Tradeoffs for Tera-scale Architectures.
M Azimi, N Cherukuri, DN Jayasimha, A Kumar, P Kundu, S Park, ...
Intel technology journal 11 (3), 2007
1232007
Towards a communication characterization methodology for parallel applications
S Chodnekar, V Srinivasan, AS Vaidya, A Sivasubramaniam, CR Das
Proceedings Third International Symposium on High-Performance Computer …, 1997
751997
SIMD divergence optimization through intra-warp compaction
AS Vaidya, A Shayesteh, DH Woo, R Saharoy, M Azimi
Proceedings of the 40th Annual International Symposium on Computer …, 2013
482013
Impact of virtual channels and adaptive routing on application performance
AS Vaidya, A Sivasubramaniam, CR Das
IEEE Transactions on Parallel and Distributed Systems 12 (2), 223-237, 2001
482001
LAPSES: A recipe for high performance adaptive router design
AS Vaidya, A Sivasubramaniam, CR Das
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
391999
Investigating QoS support for traffic mixes with the MediaWorm router
KH Yum, A Vaidya, CR Das, A Sivasubramaniam
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
372000
Performance benefits of virtual channels and adaptive routing: An application-driven study
AS Vaidya, A Sivasubramaniam, CR Das
Proceedings of the 11th international conference on Supercomputing, 140-147, 1997
361997
Conditional and vectored system management interrupts
M Ayyar, I Schoinas, RR Menon, A Vaidya, A Kumar
US Patent 7,433,985, 2008
332008
Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor
AS Vaidya, A Shayesteh, DH Woo, S Saharoy, M Azimi
US Patent 9,606,797, 2017
242017
MediaWorm: A QoS capable router architecture for clusters
KH Yum, EJ Kim, CR Das, AS Vaidya
IEEE transactions on parallel and distributed systems 13 (12), 1261-1274, 2002
232002
Modular decoupled crossbar for on-chip router
D Park, A Vaidya, A Kumar, M Azimi
US Patent 9,674,114, 2017
212017
Flexible and Adaptive On-Chip Interconnect for Tera-Scale Architectures
M Azimi, D Dai, A Kumar, A Meija, D Park, R Saharoy, AS Vaidya
Intel Technology Journal 13 (4), 62-77, 2009
192009
Method and apparatus for hierarchical routing in multiprocessor mesh-based systems
AS Vaidya, DN Jayasimha
US Patent App. 12/113,281, 2009
182009
A testbed for evaluation of fault-tolerant routing in multiprocessor interconnection networks
AS Vaidya, CR Das, A Sivasubramaniam
IEEE Transactions on Parallel and Distributed Systems 10 (10), 1052-1066, 1999
161999
MoDe-X: Microarchitecture of a layout-aware modular decoupled crossbar for on-chip interconnects
D Park, A Vaidya, A Kumar, M Azimi
IEEE transactions on computers 63 (3), 622-636, 2012
102012
On-Chip Interconnect Trade-Offs for Tera-Scale Many-Core Processors
M Azimi, D Dai, A Kumar, AS Vaidya
Designing Network On-Chip Architectures in the Nanoscale Era, 2010
52010
FPGA-based prototyping of A 2D mesh/torus on-chip interconnect
D Dai, A Vaidya, R Saharoy, S Park, D Park, HL Thantry, R Plate, E Maas, ...
Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010
12010
SYNTHESIS OF 2-(2'-METHOXY-4'-METHYLPHENYL)-6-METHYLHEPT-5-EN-4-ONE & 2-(2'-METHOXY-5'-METHYLPHENYL)-6-METHYL-HEPT-4-EN-4-ONE
PP Sane
11978
On Chip Network Routing for Tera-Scale Architectures
AS Vaidya, M Azimi, A Kumar
Routing Algorithms in Networks-on-Chip, 379-410, 2014
2014
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