| Timing optimization through clock skew scheduling IS Kourtev, B Taskin, EG Friedman Springer US, 2009 | 129 | 2009 |
| Clock skew scheduling for improved reliability via quadratic programming IS Kourtev, EG Friedman 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 75 | 1999 |
| Delay insertion method in clock skew scheduling B Taskin, IS Kourtev Proceedings of the 2005 international symposium on Physical design, 47-54, 2005 | 51 | 2005 |
| A single latch, high speed double-edge triggered flip-flop (DETFF) TA Johnson, IS Kourtev ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and …, 2001 | 42 | 2001 |
| Timing-driven physical design for VLSI circuits using resonant rotary clocking B Taskin, J Wood, IS Kourtev 2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006 | 29 | 2006 |
| Substrate coupling in digital circuits in mixed-signal smart-power systems RM Secareanu, S Warner, S Seabridge, C Burke, J Becerra, TE Watrobski, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (1), 67-78, 2004 | 23 | 2004 |
| A 64-way VLIW/SIMD FPGA architecture and design flow AK Jones, R Hoare, IS Kourtev, J Fazekas, D Kusic, J Foster, S Boddie, ... Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004 | 21 | 2004 |
| Simultaneous clock scheduling and buffered clock tree synthesis IS Kourtev, EG Friedman 1997 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 1812-1815, 1997 | 21 | 1997 |
| Reduced dynamic swing domino logic R Mader, I Kourtev Proceedings of the 13th ACM Great Lakes symposium on VLSI, 33-36, 2003 | 19 | 2003 |
| A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations IS Kourtev, EG Friedman Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No. 99TH8454 …, 1999 | 16 | 1999 |
| Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits B Taskin, IS Kourtev IEEE transactions on very large scale integration (VLSI) systems 12 (1), 12-27, 2004 | 15 | 2004 |
| Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits R Mader, EG Friedman, A Litman, IS Kourtev 2002 IEEE International Symposium on Circuits and Systems (ISCAS) 1, I-I, 2002 | 13 | 2002 |
| Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew B Taskin, IS Kourtev Proceedings of the 8th ACM/IEEE international workshop on Timing issues in …, 2002 | 12 | 2002 |
| Synthesis of clock tree topologies to implement nonzero clock skew schedule IS Kourtev, EG Friedman IEE Proceedings-Circuits, Devices and Systems 146 (6), 321-326, 1999 | 12 | 1999 |
| Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits B Taskin, IS Kourtev 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 11 | 2004 |
| The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment RM Secareanu, IS Kourtev, J Becerra, TE Watrobski, C Morton, W Staub, ... 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD …, 1999 | 10 | 1999 |
| Noise immunity of digital circuits in mixed-signal smart power systems RM Secareanu, IS Kourtev, J Becerra, TE Watrobski, C Morton, W Staub, ... Proceedings Ninth Great Lakes Symposium on VLSI, 314-317, 1999 | 10 | 1999 |
| Topological synthesis of clock trees for VLSI-based DSP systems IS Kourtev, EG Friedman 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and …, 1997 | 10 | 1997 |
| LURU: global-scope FPGA technology mapping with content-addressable memories JM Lucas, R Hoare, IS Kourtev, AK Jones Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004 | 8 | 2004 |
| Topological Synthesis of Clock Tress with Non-zero Clock Skew IS Kourtev Proceedings of ACM/IEEE International Workshop on Timing Issues in the …, 1997 | 8 | 1997 |
