Sébastien Le Beux
Sébastien Le Beux
Verified email at encs.concordia.ca - Homepage
Cited by
Cited by
A model-driven design framework for massively parallel embedded systems
A Gamatié, S Le Beux, É Piel, R Ben Atitallah, A Etien, P Marquet, ...
ACM Transactions on Embedded Computing Systems (TECS) 10 (4), 1-36, 2011
Optical ring network-on-chip (ORNoC): Architecture and design methodology
S Le Beux, J Trajkovic, I O'Connor, G Nicolescu, G Bois, P Paulin
2011 Design, Automation & Test in Europe, 1-6, 2011
Chameleon: Channel efficient optical network-on-chip
S Le Beux, H Li, I O'Connor, K Cheshmi, X Liu, J Trajkovic, G Nicolescu
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
A model driven design framework for high performance embedded systems
A Gamatié, S Le Beux, É Piel, A Etien, RB Atitallah, P Marquet, ...
INRIA, 2008
Full-adder circuit design based on all-spin logic device
Q An, L Su, JO Klein, S Le Beux, I O'Connor, W Zhao
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
Thermal aware design method for vcsel-based on-chip optical interconnect
H Li, A Fourmigue, S Le Beux, X Letartre, I O'Connor, G Nicolescu
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
Layout guidelines for 3D architectures including optical ring network-on-chip (ORNoC)
S Le Beux, J Trajkovic, I O'Connor, G Nicolescu
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 242-247, 2011
A case study of signal-to-noise ratio in ring-based optical networks-on-chip
LHK Duong, M Nikdast, S Le Beux, J Xu, X Wu, Z Wang, P Yang
IEEE Design & Test 31 (5), 55-65, 2014
Reduction methods for adapting optical network on chip topologies to 3D architectures
S Le Beux, I O’Connor, G Nicolescu, G Bois, P Paulin
Microprocessors and Microsystems 37 (1), 87-98, 2013
Optical crossbars on chip, a comparative study based on worst‐case losses
S Le Beux, H Li, G Nicolescu, J Trajkovic, I O'Connor
Concurrency and Computation: Practice and Experience 26 (15), 2492-2503, 2014
Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles
S Le Beux
Université des Sciences et Technologie de Lille-Lille I, 2007
Multi-optical network-on-chip for large scale MPSoC
S Le Beux, J Trajkovic, I O'Connor, G Nicolescu, G Bois, P Paulin
IEEE embedded systems letters 2 (3), 77-80, 2010
Coherent and incoherent crosstalk noise analyses in interchip/intrachip optical interconnection networks
LHK Duong, Z Wang, M Nikdast, J Xu, P Yang, Z Wang, Z Wang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (7 …, 2016
Combining mapping and partitioning exploration for NoC-based embedded systems
S Le Beux, G Bois, G Nicolescu, Y Bouchebaba, M Langevin, P Paulin
Journal of Systems Architecture 56 (7), 223-232, 2010
Hardware/software exploration for an anti-collision radar system
S Le Beux, V Gagne, EM Aboulhamid, P Marquet, JL Dekeyser
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006
Coherent crosstalk noise analyses in ring-based optical interconnects
LHK Duong, M Nikdast, J Xu, Z Wang, Y Thonnart, S Le Beux, P Yang, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 501-506, 2015
Optimizing configuration and application mapping for MPSoC architectures
S Le Beux, G Nicolescu, G Bois, Y Bouchebaba, M Langevin, P Paulin
2009 NASA/ESA Conference on Adaptive Hardware and Systems, 474-481, 2009
MpNoC design: Modeling and simulation
S Duquennoy, S Le Beux, P Marquet, S Meftali, JL Dekeyser
15th IP based SoC Design Conference, 229-232, 2006
Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC
J Luo, A Elantably, VD Pham, C Killian, D Chillet, S Le Beux, O Sentieys, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Ambipolar double-gate FET binary-decision-diagram (Am-BDD) for reconfigurable logic cells
K Jabeur, N Yakymets, I O'Connor, S Le Beux
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 162-168, 2011
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