Neil Veira
Neil Veira
Verified email at eecg.toronto.edu
Title
Cited by
Cited by
Year
Astraea: A decentralized blockchain oracle
J Adler, R Berryhill, A Veneris, Z Poulos, N Veira, A Kastania
2018 IEEE international conference on internet of things (IThings) and IEEE …, 2018
1052018
On public decentralized ledger oracles via a paired-question protocol
M Merlini, N Veira, R Berryhill, A Veneris
2019 IEEE International Conference on Blockchain and Cryptocurrency (ICBC …, 2019
122019
Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations.
N Veira, B Keng, K Padmanabhan, AG Veneris
IJCAI, 5218-5225, 2019
92019
Learning support sets in IC3 and Quip: The good, the bad, and the ugly
R Berryhill, A Ivrii, N Veira, A Veneris
2017 Formal Methods in Computer Aided Design (FMCAD), 140-147, 2017
62017
On public crowdsource-based mechanisms for a decentralized blockchain oracle
K Nelaturu, J Adler, M Merlini, R Berryhill, N Veira, Z Poulos, A Veneris
IEEE Transactions on Engineering Management 67 (4), 1444-1458, 2020
52020
Suspect set prediction in RTL bug hunting
N Veira, Z Poulos, A Veneris
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
42018
Generating realistic sequences of customer-level transactions for retail datasets
T Doan, N Veira, B Keng
2018 IEEE International Conference on Data Mining Workshops (ICDMW), 820-827, 2018
32018
Learning lemma support graphs in quip and IC3
R Berryhill, N Veira, A Veneris, Z Poulos
2017 IEEE 2nd International Verification and Security Workshop (IVSW), 105-110, 2017
32017
Suspect2vec: A suspect prediction model for directed RTL debugging
N Veira, Z Poulos, A Veneris
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
22019
Method and system for generating aspects associated with a future event for a subject
B Keng, N Veira, T Doan
US Patent App. 16/662,370, 2021
2021
Searching for Bugs Using Probabilistic Suspect Implications
N Veira, Z Poulos, A Veneris
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
2020
Novel Approaches to Register Transfer Level Debugging and Embedding Representations for Knowledge Base Completion
N Veira
University of Toronto (Canada), 2019
2019
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Articles 1–12