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Zeshan Chishti
Zeshan Chishti
Staff Research Scientist, Intel Corporation
Verified email at intel.com
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Cited by
Cited by
Year
Optimizing replication, communication, and capacity allocation in CMPs
Z Chishti, MD Powell, TN Vijaykumar
32nd International Symposium on Computer Architecture (ISCA'05), 357-368, 2005
4092005
Trading off cache capacity for reliability to enable low voltage operation
C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu
ACM SIGARCH computer architecture news 36 (3), 203-214, 2008
3592008
Distance associativity for high-performance energy-efficient non-uniform cache architectures
Z Chishti, MD Powell, TN Vijaykumar
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
2832003
Reducing cache power with low-cost, multi-bit error-correcting codes
C Wilkerson, AR Alameldeen, Z Chishti, W Wu, D Somasekhar, S Lu
Proceedings of the 37th annual international symposium on Computer …, 2010
2762010
Improving DRAM performance by parallelizing refreshes with accesses
KKW Chang, D Lee, Z Chishti, AR Alameldeen, C Wilkerson, Y Kim, ...
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
2332014
Improving cache lifetime reliability at ultra-low voltages
Z Chishti, AR Alameldeen, C Wilkerson, W Wu, SL Lu
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
2092009
Energy-efficient cache design using variable-strength error-correcting codes
AR Alameldeen, I Wagner, Z Chishti, W Wu, C Wilkerson, SL Lu
ACM SIGARCH Computer Architecture News 39 (3), 461-472, 2011
2082011
Usimm: the utah simulated memory module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
University of Utah, Tech. Rep, 1-24, 2012
1802012
Efficiently prefetching complex address patterns
M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ...
2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015
1472015
Transparent hardware management of stacked dram as part of memory
J Sim, AR Alameldeen, Z Chishti, C Wilkerson, H Kim
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 13-24, 2014
1332014
DRAM refresh mechanisms, penalties, and trade-offs
I Bhati, MT Chang, Z Chishti, SL Lu, B Jacob
IEEE Transactions on Computers 65 (1), 108-121, 2015
1302015
Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions
I Bhati, Z Chishti, SL Lu, B Jacob
Proceedings of the 42nd Annual International Symposium on Computer …, 2015
1202015
Path confidence based lookahead prefetching
J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
1182016
Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers
SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ...
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1152014
Hardware support for thread scheduling on multi-core processors
AR Alameldeen, ZA Chishti
US Patent 8,276,142, 2012
792012
Aggregated write back in a direct mapped two level memory
Z Wang, CB Wilkerson, ZA Chishti
US Patent 10,496,544, 2019
652019
Techniques to reduce memory cell refreshes for a memory device
ZA Chishti, IS Bhati, SLL Lu
US Patent 9,418,723, 2016
622016
Adaptive cache design to enable reliable low-voltage operation
AR Alameldeen, Z Chishti, C Wilkerson, W Wu, SL Lu
IEEE Transactions on Computers 60 (1), 50-63, 2010
602010
Method and apparatus for using cache memory in a system that supports a low power state
CB Wilkerson, AR Alameldeen, ZA Chishti, D Somasekhar, W Wu, SL Lu
US Patent 8,640,005, 2014
572014
Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads
R Wang, AJ Herdrich, YC Liu, HH Hum, JS Park, CJ Hughes, ...
US Patent 10,817,425, 2020
562020
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