| Parameter variations and impact on circuits and microarchitecture S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De Proceedings of the 40th annual Design Automation Conference, 338-342, 2003 | 1910 | 2003 |
| Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage JW Tschanz, JT Kao, SG Narendra, R Nair, DA Antoniadis, ... IEEE Journal of Solid-State Circuits 37 (11), 1396-1402, 2002 | 996 | 2002 |
| System and method for securing financial transactions T Spitzer, P Tadepalli, S Narendra US Patent App. 11/144,363, 2005 | 629 | 2005 |
| Scaling of stack effect and its application for leakage reduction S Narendra, V De, D Antoniadis, A Chandrakasan, S Borkar Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 474 | 2001 |
| Leakage in nanometer CMOS technologies SG Narendra, AP Chandrakasan Springer Science & Business Media, 2006 | 441 | 2006 |
| A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package P Hazucha, G Schrom, J Hahn, BA Bloechel, P Hack, GE Dermer, ... IEEE Journal of Solid-State Circuits 40 (4), 838-845, 2005 | 414 | 2005 |
| Dynamic sleep transistor and body bias for active leakage power control of microprocessors JW Tschanz, SG Narendra, Y Ye, BA Bloechel, S Borkar, V De IEEE Journal of Solid-State Circuits 38 (11), 1838-1845, 2003 | 398 | 2003 |
| Subthreshold leakage modeling and reduction techniques J Kao, S Narendra, A Chandrakasan Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 375 | 2002 |
| Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors J Tschanz, S Narendra, Z Chen, S Borkar, M Sachdev, V De Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 349 | 2001 |
| Electronic transaction card SG Narendra, TN Spitzer, P Tadepalli US Patent 7,581,678, 2009 | 337 | 2009 |
| Mobile phone with electronic transaction card SG Narendra, P Tadepalli, TN Spitzer US Patent 7,828,214, 2010 | 309 | 2010 |
| Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 275 | 2007 |
| MTCMOS hierarchical sizing based on mutual exclusive discharge patterns J Kao, S Narendra, A Chandrakasan Proceedings of the 35th annual Design Automation Conference, 495-500, 1998 | 271 | 1998 |
| Electronic transaction card powered by mobile device SG Narendra, P Tadepalli, TN Spitzer US Patent 7,954,716, 2011 | 261 | 2011 |
| Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs A Keshavarzi, S Ma, S Narendra, B Bloechel, K Mistry, T Ghani, S Borkar, ... Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 255 | 2001 |
| Multiple well transistor circuits having forward body bias VK De, A Keshavarzi, SG Narendra, SY Borkar US Patent 6,218,895, 2001 | 234 | 2001 |
| Power negotation for small rfid card SG Narendra, P Tadepalli, S Chakraborty US Patent App. 12/188,382, 2010 | 231 | 2010 |
| Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/CMOS process P Hazucha, T Karnik, S Walstra, BA Bloechel, JW Tschanz, J Maiz, ... IEEE Journal of Solid-State Circuits 39 (9), 1536-1543, 2004 | 222 | 2004 |
| Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors JW Tschanz, S Narendra, R Nair, V De IEEE Journal of Solid-State Circuits 38 (5), 826-829, 2003 | 202 | 2003 |
| Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS S Narendra, V De, S Borkar, DA Antoniadis, AP Chandrakasan IEEE Journal of Solid-State Circuits 39 (3), 501-510, 2004 | 200 | 2004 |
