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Naresh Shanbhag
Naresh Shanbhag
Professor of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
Verified email at illinois.edu - Homepage
Title
Cited by
Cited by
Year
High-throughput LDPC decoders
MM Mansour, NR Shanbhag
IEEE transactions on very large scale integration (VLSI) Systems 11 (6), 976-996, 2003
7592003
Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care
HU Chung, BH Kim, JY Lee, J Lee, Z Xie, EM Ibler, KH Lee, A Banks, ...
Science 363 (6430), eaau0780, 2019
5952019
High-speed architectures for Reed-Solomon decoders
DV Sarwate, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (5), 641-655, 2001
4772001
Soft digital signal processing
R Hegde, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (6), 813-823, 2001
3602001
Soft-error-rate-analysis (SERA) methodology
M Zhang, NR Shanbhag
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
3522006
A 640-Mb/s 2048-bit programmable LDPC decoder chip
MM Mansour, NR Shanbhag
IEEE Journal of Solid-State Circuits 41 (3), 684-698, 2006
3152006
Energy-efficient signal processing via algorithmic noise-tolerance
R Hegde, NR Shanbhag
Proceedings of the 1999 international symposium on Low power electronics and …, 1999
2951999
A coding framework for low-power address and data busses
S Ramprasad, NR Shanbhag, IN Hajj
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (2), 212-221, 1999
2911999
Sequential element design with built-in soft error resilience
M Zhang, S Mitra, TM Mak, N Seifert, NJ Wang, Q Shi, KS Kim, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (12 …, 2006
2832006
Low-power VLSI decoder architectures for LDPC codes
MM Mansour, NR Shanbhag
Proceedings of the 2002 international symposium on Low power electronics and …, 2002
2692002
Coding for system-on-chip networks: a unified framework
SR Sridhara, NR Shanbhag
Proceedings of the 41st annual Design Automation Conference, 103-106, 2004
2682004
Reliable low-power digital signal processing via reduced precision redundancy
B Shim, SR Sridhara, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 497-510, 2004
2552004
A multi-functional in-memory inference processor using a standard 6T SRAM array
M Kang, SK Gonugondla, A Patil, NR Shanbhag
IEEE Journal of Solid-State Circuits 53 (2), 642-655, 2018
2272018
Coupling-driven signal encoding scheme for low-power interface design
KW Kim, N Shanbhag, CL Liu, SM Kang
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
2182000
Energy-efficient soft error-tolerant digital signal processing
B Shim, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (4), 336-348, 2006
2052006
Stochastic computation
NR Shanbhag, RA Abdallah, R Kumar, DL Jones
Proceedings of the 47th Design Automation Conference, 859-864, 2010
2032010
A 42pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training
SK Gonugondla, M Kang, N Shanbhag
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2018
2012018
An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM
M Kang, MS Keel, NR Shanbhag, S Eilert, K Curewitz
2014 IEEE International Conference on Acoustics, Speech and Signal …, 2014
1972014
Toward achieving energy efficiency in presence of deep submicron noise
R Hegde, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 379-391, 2000
1822000
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
JE Jaussi, G Balamurugan, DR Johnson, B Casper, A Martin, J Kennedy, ...
IEEE Journal of Solid-State Circuits 40 (1), 80-88, 2005
1482005
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