| Performance modelling and dynamic scheduling on heterogeneous-ISA multi-core architectures NK Boran, DK Yadav, R Iyer VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 5 | 2019 |
| Performance modelling of heterogeneous ISA multicore architectures NK Boran, RP Meghwal, K Sharma, B Kumar, V Singh 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | 4 | 2016 |
| Fine-Grained Scheduling in Heterogeneous-ISA Architectures NK Boran, S Rathore, M Udeshi, V Singh IEEE Computer Architecture Letters 20 (1), 9-12, 2020 | 2 | 2020 |
| Classification based scheduling in heterogeneous ISA architectures NK Boran, DK Yadav, R Iyer 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6, 2020 | 2 | 2020 |
| On Disabling Prefetcher to Amplify Cache Side Channels NK Boran, K Pinto, B Menezes 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-6, 2021 | 1 | 2021 |
| PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning NK Boran, P Joshi, V Singh Proceedings of the 19th International Conference on Security and …, 2022 | | 2022 |
| Architecting High Performance, Energy Efficient & Secured Multi-Core Systems NK Boran Indian Institute of Technology Bombay Mumbai, 2021 | | 2021 |
