JCS Woo
JCS Woo
Verified email at ee.ucla.edu
Title
Cited by
Cited by
Year
The impact of high-/spl kappa/gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
B Cheng, M Cao, R Rao, A Inani, PV Voorde, WM Greene, JMC Stork, ...
IEEE Transactions on Electron Devices 46 (7), 1537-1544, 1999
4301999
The tunnel source (PNPN) n-MOSFET: A novel high performance transistor
V Nagavarapu, R Jhaveri, JCS Woo
IEEE Transactions on Electron Devices 55 (4), 1013-1019, 2008
3122008
A MEMS based amperometric detector for E. coli bacteria using self-assembled monolayers
JJ Gau, EH Lan, B Dunn, CM Ho, JCS Woo
Biosensors and Bioelectronics 16 (9-12), 745-755, 2001
2852001
High-gain lateral bipolar action in a MOSFET structure
S Verdonckt-Vandebroek, SS Wong, JCS Woo, PK Ko
IEEE Transactions on Electron Devices 38 (11), 2487-2496, 1991
2461991
Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x/PMOS
DK Nayak, JCS Woo, JS Park, K Wang, KP MacWilliams
IEEE Electron Device Letters 12 (4), 154-156, 1991
2441991
Salicidation process using NiSi and its device application
F Deng, RA Johnson, PM Asbeck, SS Lau, WB Dubbelday, T Hsiao, ...
Journal of applied physics 81 (12), 8047-8051, 1997
2221997
Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor
R Jhaveri, V Nagavarapu, JCS Woo
IEEE Transactions on Electron Devices 58 (1), 80-86, 2010
2172010
Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides
D Dimitropoulos, R Jhaveri, R Claps, JCS Woo, B Jalali
Applied Physics Letters 86 (7), 071115, 2005
2172005
High‐mobility p‐channel metal‐oxide‐semiconductor field‐effect transistor on strained Si
DK Nayak, JCS Woo, JS Park, KL Wang, KP MacWilliams
Applied physics letters 62 (22), 2853-2855, 1993
2001993
Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS
SD Kim, CM Park, JCS Woo
IEEE Transactions on Electron Devices 49 (10), 1748-1754, 2002
1852002
Complementary field effect transistors having strained superlattice structure
KL Wang, JC Woo
US Patent 5,155,571, 1992
1811992
Wet oxidation of GeSi strained layers by rapid thermal processing
DK Nayak, K Kamjoo, JS Park, JCS Woo, KL Wang
Applied physics letters 57 (4), 369-371, 1990
1511990
Large scale pattern graphene electrode for high performance in transparent organic single crystal field-effect transistors
W Liu, BL Jackson, J Zhu, CQ Miao, CH Chung, YJ Park, K Sun, J Woo, ...
Acs Nano 4 (7), 3927-3932, 2010
1362010
TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling
SD Kim, H Wada, JCS Woo
IEEE transactions on Semiconductor Manufacturing 17 (2), 192-200, 2004
1322004
Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis
SD Kim, CM Park, JCS Woo
IEEE Transactions on Electron Devices 49 (3), 467-472, 2002
1322002
Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing
HY Chang, B Adams, PY Chien, J Li, JCS Woo
IEEE Transactions on Electron Devices 60 (1), 92-96, 2012
1312012
Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation
SD Kim, CM Park, JCS Woo
IEEE Transactions on Electron Devices 49 (3), 457-466, 2002
1192002
Rapid thermal oxidation of GeSi strained layers
D Nayak, K Kamjoo, JCS Woo, JS Park, KL Wang
Applied physics letters 56 (1), 66-68, 1990
1041990
Contact resistance in top-gated graphene field-effect transistors
BC Huang, M Zhang, Y Wang, J Woo
Applied Physics Letters 99 (3), 032107, 2011
992011
Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K
M Song, KP MacWilliams, JCS Woo
IEEE Transactions on Electron Devices 44 (2), 268-276, 1997
991997
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Articles 1–20