| Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori A Mejia, J Flich, J Duato, SA Reinemo, T Skeie Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006 | 173 | 2006 |
| A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks J Duato, I Johnson, J Flich, F Naven, P Garcia, T Nachiondo 11th International Symposium on High-Performance Computer Architecture, 108-119, 2005 | 162 | 2005 |
| A survey and evaluation of topology-agnostic deterministic routing algorithms J Flich, T Skeie, A Mejia, O Lysne, P Lopez, A Robles, J Duato, ... IEEE Transactions on Parallel and Distributed Systems 23 (3), 405-425, 2011 | 124 | 2011 |
| Efficient unicast and multicast support for CMPs S Rodrigo, J Flich, J Duato, M Hummel 2008 41st IEEE/ACM International Symposium on Microarchitecture, 364-375, 2008 | 119 | 2008 |
| A routing methodology for achieving fault tolerance in direct networks ME Gomez, NA Nordbotten, J Flich, P Lopez, A Robles, J Duato, T Skeie, ... IEEE transactions on Computers 55 (4), 400-415, 2006 | 117 | 2006 |
| Addressing manufacturing challenges with cost-efficient fault tolerant routing S Rodrigo, J Flich, A Roca, S Medardoni, D Bertozzi, J Camacho, F Silla, ... 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 25-32, 2010 | 116 | 2010 |
| Designing network on-chip architectures in the nanoscale era J Flich, D Bertozzi CRC press, 2010 | 113 | 2010 |
| Logic-based distributed routing for NoCs J Flich, J Duato IEEE computer architecture letters 7 (1), 13-16, 2008 | 107 | 2008 |
| Region-based routing: An efficient routing mechanism to tackle unreliable hardware in network on chips J Flich, A Mejia, P López, J Duato First International Symposium on Networks-on-Chip (NOCS'07), 183-194, 2007 | 102 | 2007 |
| Region-based routing: a mechanism to support efficient routing algorithms in NoCs A Mejia, M Palesi, J Flich, S Kumar, P López, R Holsmark, J Duato IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 356-369, 2009 | 97 | 2009 |
| Path-based partitioning methods for 3D networks-on-chip with minimal adaptive routing M Ebrahimi, M Daneshtalab, P Liljeberg, J Plosila, J Flich, H Tenhunen IEEE Transactions on Computers 63 (3), 718-733, 2012 | 94 | 2012 |
| An efficient implementation of distributed routing algorithms for NoCs J Flich, S Rodrigo, J Duato Second ACM/ieee international symposium on networks-on-chip (NOCs 2008), 87-96, 2008 | 93 | 2008 |
| An efficient and deadlock-free network reconfiguration protocol O Lysne, JM Montanana, J Flich, J Duato, TM Pinkston, T Skeie IEEE Transactions on Computers 57 (6), 762-779, 2008 | 69 | 2008 |
| An efficient fault-tolerant routing methodology for meshes and tori ME Gómez, J Duato, J Flich, P Lopez, A Robles, NA Nordbotten, O Lysne, ... IEEE Computer Architecture Letters 3 (1), 3-3, 2004 | 69 | 2004 |
| Efficient implementation of distributed routing algorithms for NoCs S Rodrigo, S Medardoni, J Flich, D Bertozzi, J Duato IET computers & digital techniques 3 (5), 460-475, 2009 | 68 | 2009 |
| Efficient, scalable congestion management for interconnection networks PJ García, FJ Quiles, J Flich, J Duato, I Johnson, F Naven IEEE Micro 26 (5), 52-66, 2006 | 68 | 2006 |
| LASH-TOR: A generic transition-oriented routing algorithm T Skeie, O Lysne, J Flich, P Lopez, A Robles, J Duato Proceedings. Tenth International Conference on Parallel and Distributed …, 2004 | 65 | 2004 |
| Dynamic evolution of congestion trees: Analysis and impact on switch architecture PJ García, J Flich, J Duato, I Johnson, FJ Quiles, F Naven High Performance Embedded Architectures and Compilers: First International …, 2005 | 62 | 2005 |
| Deadlock-free routing in infiniband/sup tm/through destination renaming P Lopez, J Flich, J Duato International Conference on Parallel Processing, 2001., 427-434, 2001 | 62 | 2001 |
| Effective methodology for deadlock-free minimal routing in InfiniBand networks JC Sancho, A Robles, J Flich, P Lopez, J Duato Proceedings International Conference on Parallel Processing, 409-418, 2002 | 61 | 2002 |
Olav LysneProfessor, Simula Research LaboratoryVerified email at simula.no
