Maksim Jenihhin

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Jaan RaikTallinn University of TechnologyVerified email at taltech.ee
Raimund UbarProfessor of Computer Engineering, Tallinn University of TechnologyVerified email at pld.ttu.ee
Gert JervanSchool of IT, Tallinn University of Technology (TalTech)Verified email at taltech.ee
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringVerified email at polito.it
Peeter EllerveeProfessor of Computer Engineering, Tallinn University of TechnologyVerified email at ati.ttu.ee
Artur JutmanTalTechVerified email at pld.ttu.ee
Sergei Kostinresearcher of Computer Science, Tallinn University of TechnologyVerified email at ati.ttu.ee
Zebo PengProfessor of Computer Systems, Linkoping UniversityVerified email at liu.se
Franco FummiProfessor of Computer Engineering, Universita' di VeronaVerified email at univr.it
Graziano PravadelliFull professor, University of Verona, ItalyVerified email at univr.it
Sergei DevadzeTallinn University of TechnologyVerified email at pld.ttu.ee
Uljana Reinsaluresearcher at Tallinn University of TechnologyVerified email at ati.ttu.ee
Giovanni SquilleroPolitecnico di TorinoVerified email at polito.it
Petru ElesProfessor of Computer Systems, Linkoping UniversityVerified email at liu.se
Guilherme Cardoso MedeirosTU DelftVerified email at tudelft.nl
Witold A. PleskaczWarsaw University of Technology, PolandVerified email at imio.pw.edu.pl
Ernesto SanchezAssociate Professor at Politecnico di TorinoVerified email at polito.it
Wuttke, Heinz-DietrichIlmenau University of TechnologyVerified email at tu-ilmenau.de
Goerschwin FeyHamburg University of TechnologyVerified email at tuhh.de
Hideo Fujiwara 藤原秀雄Professor Emeritus, NAISTVerified email at fujiwaralab.net

Maksim Jenihhin

Dept. of Computer Systems, Tallinn University of Technology

Verified email at ati.ttu.ee

nanoelectronics reliability system dependability verification and debug fault tolerance and resilience EDA methodologies


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Test time minimization for hybrid BIST of core-based systems Jervan, Eles, Peng, Ubar, Jenihhin 2003 Test Symposium, 318-323, 2003	51	2003
A survey on UAV computing platforms: A hardware reliability perspective F Ahmed, M Jenihhin Sensors 22 (16), 6286, 2022	27	2022
Hybrid BIST time minimization for core-based systems with STUMPS architecture G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003	25	2003
Combining dynamic slicing and mutation operators for ESL correction U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ... 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012	22	2012
Identification and rejuvenation of nbti-critical logic paths in nanoscale circuits M Jenihhin, G Squillero, TS Copetti, V Tihhomirov, S Kostin, M Gaudesi, ... Journal of Electronic Testing 32, 273-289, 2016	21	2016
A scalable model based RTL framework zamiaCAD for static analysis A Tšepurov, G Bartsch, R Dorsch, M Jenihhin, J Raik, V Tihhomirov 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012	20	2012
Code coverage analysis using high-level decision diagrams J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008	19	2008
Understanding multidimensional verification: Where functional meets non-functional X Lai, A Balakrishnan, T Lange, M Jenihhin, T Ghasempouri, J Raik, ... Microprocessors and microsystems 71, 102867, 2019	17	2019
Towards multidimensional verification: Where functional meets non-functional M Jenihhin, X Lai, T Ghasempouri, J Raik 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2018	17	2018
Hierarchical identification of NBTI-critical gates in nanoscale logic S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti 2014 15th Latin American Test Workshop-LATW, 1-6, 2014	15	2014
Diagnostic modeling of digital systems with multi-level decision diagrams R Ubar, J Raik, A Jutman, M Jenihhin Geographic Information Systems: Concepts, Methodologies, Tools, and …, 2013	15	2013
Temporally extended high-level decision diagrams for PSL assertions simulation M Jenihhin, J Raik, A Chepurov, R Ubar 2008 13th European Test Symposium, 61-68, 2008	15	2008
Fast and fair computation offloading management in a swarm of drones using a rating-based federated learning approach D Rahbari, MM Alam, Y Le Moullec, M Jenihhin IEEE Access 9, 113832-113849, 2021	14	2021
Mutation analysis for SystemC designs at TLM V Guarnieri, N Bombieri, G Pravadelli, F Fummi, H Hantson, J Raik, ... 2011 12th Latin American Test Workshop (LATW), 1-6, 2011	14	2011
Mixed hierarchical-functional fault models for targeting sequential cores J Raik, R Ubar, T Viilukas, M Jenihhin Journal of Systems Architecture 54 (3-4), 465-477, 2008	14	2008
Composing graph theory and deep neural networks to evaluate seu type soft error effects A Balakrishnan, T Lange, M Glorieux, D Alexandrescu, M Jenihhin 2020 9th Mediterranean Conference on Embedded Computing (MECO), 1-5, 2020	13	2020
High-level decision diagram manipulations for code coverage analysis K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ... 2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008	13	2008
Assertion checking with PSL and high-level decision diagrams M Jenihhin, J Raik, A Chepurov, R Ubar IEEE WRTLT'07, 12-13, 2007	13	2007
Special session: AutoSoC-a suite of open-source automotive SoC benchmarks FA da Silva, AC Bagbaba, A Ruospo, R Mariani, G Kanawati, E Sanchez, ... 2020 IEEE 38th VLSI Test Symposium (VTS), 1-9, 2020	12	2020
Challenges of reliability assessment and enhancement in autonomous systems M Jenihhin, MS Reorda, A Balakrishnan, D Alexandrescu 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019	12	2019

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