| Test time minimization for hybrid BIST of core-based systems G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin Journal of Computer Science and Technology 21, 907-912, 2006 | 50 | 2006 |
| Hybrid BIST time minimization for core-based systems with STUMPS architecture G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 25 | 2003 |
| Combining dynamic slicing and mutation operators for ESL correction U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ... 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 22 | 2012 |
| Identification and rejuvenation of nbti-critical logic paths in nanoscale circuits M Jenihhin, G Squillero, TS Copetti, V Tihhomirov, S Kostin, M Gaudesi, ... Journal of Electronic Testing 32, 273-289, 2016 | 20 | 2016 |
| A scalable model based RTL framework zamiaCAD for static analysis A Tšepurov, G Bartsch, R Dorsch, M Jenihhin, J Raik, V Tihhomirov 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012 | 19 | 2012 |
| Code coverage analysis using high-level decision diagrams J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008 | 18 | 2008 |
| Towards multidimensional verification: Where functional meets non-functional M Jenihhin, X Lai, T Ghasempouri, J Raik 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2018 | 16 | 2018 |
| Diagnostic modeling of digital systems with multi-level decision diagrams R Ubar, J Raik, A Jutman, M Jenihhin Geographic Information Systems: Concepts, Methodologies, Tools, and …, 2013 | 15 | 2013 |
| Understanding multidimensional verification: Where functional meets non-functional X Lai, A Balakrishnan, T Lange, M Jenihhin, T Ghasempouri, J Raik, ... Microprocessors and microsystems 71, 102867, 2019 | 14 | 2019 |
| Hierarchical identification of NBTI-critical gates in nanoscale logic S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti 2014 15th Latin American Test Workshop-LATW, 1-6, 2014 | 14 | 2014 |
| Mutation analysis for SystemC designs at TLM V Guarnieri, N Bombieri, G Pravadelli, F Fummi, H Hantson, J Raik, ... 2011 12th Latin American Test Workshop (LATW), 1-6, 2011 | 14 | 2011 |
| Temporally extended high-level decision diagrams for PSL assertions simulation M Jenihhin, J Raik, A Chepurov, R Ubar 2008 13th European Test Symposium, 61-68, 2008 | 14 | 2008 |
| Mixed hierarchical-functional fault models for targeting sequential cores J Raik, R Ubar, T Viilukas, M Jenihhin Journal of Systems Architecture 54 (3-4), 465-477, 2008 | 13 | 2008 |
| Constraint-based test pattern generation at the register-transfer level T Viilukas, J Raik, M Jenihhin, R Ubar, A Krivenko 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 12 | 2010 |
| High-level decision diagram manipulations for code coverage analysis K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ... 2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008 | 12 | 2008 |
| Assertion checking with PSL and high-level decision diagrams M Jenihhin, J Raik, A Chepurov, R Ubar IEEE WRTLT'07, 12-13, 2007 | 12 | 2007 |
| Spice-inspired fast gate-level computation of nbti-induced delays in nanoscale logic S Kostin, J Raik, R Ubar, M Jenihhin, T Copetti, F Vargas, LB Poehls 2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015 | 11 | 2015 |
| EEG analyzer prototype based on FPGA M Jenihhin, M Gorev, V Pesonen, D Mihhailov, P Ellervee, H Hinrikus, ... 2011 7th International Symposium on Image and Signal Processing and Analysis …, 2011 | 10 | 2011 |
| Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC WA Pleskacz, M Jenihhin, J Raik, M Rakowski, R Ubar, W Kuzmicz 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 10 | 2008 |
| Hierarchical calculation of malicious faults for evaluating the fault-tolerance R Ubar, S Devadze, M Jenihhin, J Raik, G Jervan, P Ellervee 4th IEEE International Symposium on Electronic Design, Test and Applications …, 2008 | 10 | 2008 |
Jaan RaikTallinn University of TechnologyVerified email at taltech.ee
