Maksim Jenihhin
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Test time minimization for hybrid BIST of core-based systems
Jervan, Eles, Peng, Ubar, Jenihhin
2003 Test Symposium, 318-323, 2003
A survey on UAV computing platforms: A hardware reliability perspective
F Ahmed, M Jenihhin
Sensors 22 (16), 6286, 2022
Hybrid BIST time minimization for core-based systems with STUMPS architecture
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
Identification and rejuvenation of nbti-critical logic paths in nanoscale circuits
M Jenihhin, G Squillero, TS Copetti, V Tihhomirov, S Kostin, M Gaudesi, ...
Journal of Electronic Testing 32, 273-289, 2016
Combining dynamic slicing and mutation operators for ESL correction
U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ...
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
A scalable model based RTL framework zamiaCAD for static analysis
A Tšepurov, G Bartsch, R Dorsch, M Jenihhin, J Raik, V Tihhomirov
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
Code coverage analysis using high-level decision diagrams
J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
Understanding multidimensional verification: Where functional meets non-functional
X Lai, A Balakrishnan, T Lange, M Jenihhin, T Ghasempouri, J Raik, ...
Microprocessors and microsystems 71, 102867, 2019
Challenges of reliability assessment and enhancement in autonomous systems
M Jenihhin, MS Reorda, A Balakrishnan, D Alexandrescu
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019
Towards multidimensional verification: Where functional meets non-functional
M Jenihhin, X Lai, T Ghasempouri, J Raik
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2018
Fast and fair computation offloading management in a swarm of drones using a rating-based federated learning approach
D Rahbari, MM Alam, Y Le Moullec, M Jenihhin
IEEE Access 9, 113832-113849, 2021
Hierarchical identification of NBTI-critical gates in nanoscale logic
S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti
2014 15th Latin American Test Workshop-LATW, 1-6, 2014
Special session: AutoSoC-a suite of open-source automotive SoC benchmarks
FA da Silva, AC Bagbaba, A Ruospo, R Mariani, G Kanawati, E Sanchez, ...
2020 IEEE 38th VLSI Test Symposium (VTS), 1-9, 2020
Diagnostic modeling of digital systems with multi-level decision diagrams
R Ubar, J Raik, A Jutman, M Jenihhin
Geographic Information Systems: Concepts, Methodologies, Tools, and …, 2013
Temporally extended high-level decision diagrams for PSL assertions simulation
M Jenihhin, J Raik, A Chepurov, R Ubar
2008 13th European Test Symposium, 61-68, 2008
Deepaxe: A framework for exploration of approximation and reliability trade-offs in dnn accelerators
M Taheri, M Riazati, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik, ...
2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023
Mutation analysis for SystemC designs at TLM
V Guarnieri, N Bombieri, G Pravadelli, F Fummi, H Hantson, J Raik, ...
2011 12th Latin American Test Workshop (LATW), 1-6, 2011
Mixed hierarchical-functional fault models for targeting sequential cores
J Raik, R Ubar, T Viilukas, M Jenihhin
Journal of Systems Architecture 54 (3-4), 465-477, 2008
Composing graph theory and deep neural networks to evaluate seu type soft error effects
A Balakrishnan, T Lange, M Glorieux, D Alexandrescu, M Jenihhin
2020 9th Mediterranean Conference on Embedded Computing (MECO), 1-5, 2020
High-level decision diagram manipulations for code coverage analysis
K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ...
2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008
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