| A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme K Sohn, T Na, I Song, Y Shim, W Bae, S Kang, D Lee, H Jung, S Hyun, ... IEEE journal of solid-state circuits 48 (1), 168-177, 2012 | 69 | 2012 |
| A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme BM K Sohn, TS Na, ID Song, Y Shim, W Bae, S Kang, DS Lee, HG Jung, HK Jung ... Solid-State Circuits Conference (ISSCC), 2012 IEEE International, 38-40, 2012 | 69* | 2012 |
| 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 27 | 2017 |
| Delay-locked loop circuit and method of controlling the same TS Na, ID Song US Patent 9,077,350, 2015 | 27 | 2015 |
| Spark plug having ground electrode made of NI alloy and noble metal wear resistant portion Y Sugiyama, Y Sugiura US Patent 6,798,125, 2004 | 19 | 2004 |
| Design technologies for a 1.2 V 2.4 Gb/s/pin high capacity DDR4 SDRAM with TSVs R Oh, B Lee, SW Shin, W Bae, H Choi, I Song, YS Lee, JH Choi, CW Kim, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 16 | 2014 |
| Method for operating memory device and apparatuses performing the method I Dal Song, JH Choi, YS Yang US Patent 8,988,101, 2015 | 15 | 2015 |
| Multi-Gbit/s CMOS transimpedance amplifier with integrated photodetector for optical interconnects I Song Georgia Institute of Technology, 2004 | 15 | 2004 |
| Delay locked loop having small jitter and jitter reducing method thereof ID Song US Patent 7,583,119, 2009 | 12 | 2009 |
| Highly alignment tolerant InGaAs inverted MSM photodetector heterogeneously integrated on a differential Si CMOS receiver operating at 1 Gbps M Vrazel, JJ Chang, ID Song, KS Chung, M Brooke, NM Jokerst, A Brown, ... 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat …, 2001 | 12 | 2001 |
| Dram package, dram module including dram package, graphic module including dram package and multimedia device including dram package S Park, S InDal, J Choi, Y Kim US Patent App. 13/451,071, 2012 | 11 | 2012 |
| 17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67 Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs WJ Yun, I Song, H Jeoung, H Choi, SH Lee, JB Kim, CW Kim, JH Choi, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 10 | 2015 |
| Adaptive delay-locked loops and methods of generating clock signals using the same ID Song US Patent 7,489,171, 2009 | 9 | 2009 |
| Dual-loop two-step ZQ calibration for dynamic voltage–frequency scaling in LPDDR4 SDRAM CK Lee, J Lee, K Kim, JS Heo, JH Baek, GH Cha, D Moon, DH Lee, ... IEEE Journal of Solid-State Circuits 53 (10), 2906-2916, 2018 | 8 | 2018 |
| Memory modules with reduced rank loading and memory systems including same JK Kim, ID Song, J Choi US Patent 9,542,343, 2017 | 6 | 2017 |
| Memory chip package having optically and electrically connected chips, memory system having the same and driving method thereof JK Kim, S InDal, J Choi US Patent 9,449,653, 2016 | 6 | 2016 |
| Semiconductor memory device with signal reshaping and method of operating the same S Yong, ID Song US Patent 9,230,621, 2016 | 6 | 2016 |
| Output driver for controlling impedance and intensity of pre-emphasis driver using mode register set I Dal Song, JB Lee US Patent 7,545,164, 2009 | 6 | 2009 |
| Delay locked loop circuit for preventing failure of coarse locking KT Kang, ID Song US Patent 8,120,988, 2012 | 5 | 2012 |
| Multi-Gbit/s transimpedance amplifier with integrated photodetector for optical interconnects I Song Georgia Institute of Technology, 2004 | 5 | 2004 |
