A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme K Sohn, T Na, I Song, Y Shim, W Bae, S Kang, D Lee, H Jung, S Hyun, ... IEEE journal of solid-state circuits 48 (1), 168-177, 2012 | 77 | 2012 |
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme BM K Sohn, TS Na, ID Song, Y Shim, W Bae, S Kang, DS Lee, HG Jung, HK Jung ... Solid-State Circuits Conference (ISSCC), 2012 IEEE International, 38-40, 2012 | 77* | 2012 |
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 30 | 2017 |
Delay-locked loop circuit and method of controlling the same TS Na, ID Song US Patent 9,077,350, 2015 | 29 | 2015 |
Method for operating memory device and apparatuses performing the method I Dal Song, JH Choi, YS Yang US Patent 8,988,101, 2015 | 28 | 2015 |
Memory device for performing calibration operation LEE Hyunui, WJ Yun, YU Hye-Seung, ID Song US Patent 9,870,808, 2018 | 23 | 2018 |
Spark plug having ground electrode made of NI alloy and noble metal wear resistant portion Y Sugiyama, Y Sugiura US Patent 6,798,125, 2004 | 23* | 2004 |
Dual-loop two-step ZQ calibration for dynamic voltage–frequency scaling in LPDDR4 SDRAM CK Lee, J Lee, K Kim, JS Heo, JH Baek, GH Cha, D Moon, DH Lee, ... IEEE Journal of Solid-State Circuits 53 (10), 2906-2916, 2018 | 16 | 2018 |
Design technologies for a 1.2 V 2.4 Gb/s/pin high capacity DDR4 SDRAM with TSVs R Oh, B Lee, SW Shin, W Bae, H Choi, I Song, YS Lee, JH Choi, CW Kim, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 15 | 2014 |
Dram package, dram module including dram package, graphic module including dram package and multimedia device including dram package S Park, S InDal, J Choi, Y Kim US Patent App. 13/451,071, 2012 | 15 | 2012 |
Multi-Gbit/s CMOS transimpedance amplifier with integrated photodetector for optical interconnects I Song Georgia Institute of Technology, 2004 | 14 | 2004 |
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67 Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs WJ Yun, I Song, H Jeoung, H Choi, SH Lee, JB Kim, CW Kim, JH Choi, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 13 | 2015 |
Highly alignment tolerant InGaAs inverted MSM photodetector heterogeneously integrated on a differential Si CMOS receiver operating at 1 Gbps M Vrazel, JJ Chang, ID Song, KS Chung, M Brooke, NM Jokerst, A Brown, ... 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat …, 2001 | 13 | 2001 |
Delay locked loop having small jitter and jitter reducing method thereof ID Song US Patent 7,583,119, 2009 | 12 | 2009 |
Memory chip package having optically and electrically connected chips, memory system having the same and driving method thereof JK Kim, S InDal, J Choi US Patent 9,449,653, 2016 | 10 | 2016 |
Adaptive delay-locked loops and methods of generating clock signals using the same ID Song US Patent 7,489,171, 2009 | 10 | 2009 |
Memory modules with reduced rank loading and memory systems including same JK Kim, ID Song, J Choi US Patent 9,542,343, 2017 | 9 | 2017 |
Semiconductor memory device with signal reshaping and method of operating the same S Yong, ID Song US Patent 9,230,621, 2016 | 7 | 2016 |
Multi-Gbit/s transimpedance amplifier with integrated photodetector for optical interconnects I Song Georgia Institute of Technology, 2004 | 7 | 2004 |
An enhanced built-off-test transceiver with wide-range, self-calibration engine for 3.2 Gb/s/pin DDR4 SDRAM JW Moon, HS Yoo, H Choi, IW Park, SY Kang, JB Kim, H Chung, K Kim, ... 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 139-142, 2018 | 6 | 2018 |