| Parameterized posit arithmetic hardware generator R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018 | 42 | 2018 |
| A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ... Journal of Systems Architecture 60 (7), 592-614, 2014 | 22 | 2014 |
| Micro-architectural enhancements in distributed memory cgras for lu and qr factorizations F Merchant, A Maity, M Mahadurkar, K Vatwani, I Munje, M Krishna, ... 2015 28th International Conference on VLSI Design, 153-158, 2015 | 18 | 2015 |
| Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation ZE Rákossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014 | 18 | 2014 |
| Efficient and scalable cgra-based implementation of column-wise givens rotation ZE Rákossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay 2014 IEEE 25th International Conference on Application-Specific Systems …, 2014 | 17 | 2014 |
| A fully pipelined modular multiple precision floating point multiplier with vector support A Baluni, F Merchant, SK Nandy, S Balakrishnan 2011 International Symposium on Electronic System Design, 45-50, 2011 | 17 | 2011 |
| Efficient QR decomposition using low complexity column-wise givens rotation (CGR) F Merchant, A Chattopadhyay, G Garga, SK Nandy, R Narayan, ... 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 16 | 2014 |
| Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays D Bhattacharjee, F Merchant, A Chattopadhyay 2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016 | 15 | 2016 |
| Efficient realization of householder transform through algorithm-architecture co-design for acceleration of qr factorization F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018 | 14 | 2018 |
| Efficient realization of householder transform through algorithm-architecture co-design for acceleration of qr factorization F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018 | 14 | 2018 |
| Co-exploration of NLA kernels and specification of compute elements in distributed memory cgras M Mahadurkar, F Merchant, A Maity, K Vatwani, I Munje, N Gopalan, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 14 | 2014 |
| Accelerating BLAS and LAPACK via efficient floating point architecture design F Merchant, A Chattopadhyay, S Raha, SK Nandy, R Narayan Parallel Processing Letters 27 (03n04), 1750006, 2017 | 11 | 2017 |
| Achieving efficient QR factorization by algorithm-architecture co-design of householder transformation F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 11 | 2016 |
| Efficient realization of table look-up based double precision floating point arithmetic F Merchant, N Choudhary, SK Nandy, R Narayan 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 9 | 2016 |
| CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism R Jain, N Sharma, F Merchant, S Patkar, R Leupers arXiv preprint arXiv:2006.00364, 2020 | 7 | 2020 |
| Control-lock: Securing processor cores against software-controlled hardware trojans D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss Proceedings of the 2019 on Great Lakes Symposium on VLSI, 27-32, 2019 | 6 | 2019 |
| Platform independent 8-bit soft-core for SoPC F Merchant, S Pujari, M Patil Proceedings of the International MultiConference of Engineers and Computer …, 2009 | 6 | 2009 |
| Inter-lock: Logic encryption for processor cores beyond module boundaries D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 4 | 2019 |
| ExPAN (N) D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems S Nambi, S Ullah, A Lohana, SS Sahoo, F Merchant, A Kumar arXiv preprint arXiv:2010.12869, 2020 | 3 | 2020 |
| A secure hardware-software solution based on RISC-V, logic locking and microkernel D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ... Proceedings of the 23th International Workshop on Software and Compilers for …, 2020 | 3 | 2020 |
Rainer LeupersRWTH AachenVerified email at ice.rwth-aachen.de
