Farhad Merchant
Title
Cited by
Cited by
Year
Parameterized posit arithmetic hardware generator
R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018
422018
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ...
Journal of Systems Architecture 60 (7), 592-614, 2014
222014
Micro-architectural enhancements in distributed memory cgras for lu and qr factorizations
F Merchant, A Maity, M Mahadurkar, K Vatwani, I Munje, M Krishna, ...
2015 28th International Conference on VLSI Design, 153-158, 2015
182015
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation
ZE RŠkossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC†…, 2014
182014
Efficient and scalable cgra-based implementation of column-wise givens rotation
ZE RŠkossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay
2014 IEEE 25th International Conference on Application-Specific Systems†…, 2014
172014
A fully pipelined modular multiple precision floating point multiplier with vector support
A Baluni, F Merchant, SK Nandy, S Balakrishnan
2011 International Symposium on Electronic System Design, 45-50, 2011
172011
Efficient QR decomposition using low complexity column-wise givens rotation (CGR)
F Merchant, A Chattopadhyay, G Garga, SK Nandy, R Narayan, ...
2014 27th International Conference on VLSI Design and 2014 13th†…, 2014
162014
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays
D Bhattacharjee, F Merchant, A Chattopadhyay
2016 IFIP/IEEE International Conference on Very Large Scale Integration†…, 2016
152016
Efficient realization of householder transform through algorithm-architecture co-design for acceleration of qr factorization
F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan
IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018
142018
Efficient realization of householder transform through algorithm-architecture co-design for acceleration of qr factorization
F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan
IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018
142018
Co-exploration of NLA kernels and specification of compute elements in distributed memory cgras
M Mahadurkar, F Merchant, A Maity, K Vatwani, I Munje, N Gopalan, ...
2014 International Conference on Embedded Computer Systems: Architectures†…, 2014
142014
Accelerating BLAS and LAPACK via efficient floating point architecture design
F Merchant, A Chattopadhyay, S Raha, SK Nandy, R Narayan
Parallel Processing Letters 27 (03n04), 1750006, 2017
112017
Achieving efficient QR factorization by algorithm-architecture co-design of householder transformation
F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan
2016 29th International Conference on VLSI Design and 2016 15th†…, 2016
112016
Efficient realization of table look-up based double precision floating point arithmetic
F Merchant, N Choudhary, SK Nandy, R Narayan
2016 29th International Conference on VLSI Design and 2016 15th†…, 2016
92016
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
R Jain, N Sharma, F Merchant, S Patkar, R Leupers
arXiv preprint arXiv:2006.00364, 2020
72020
Control-lock: Securing processor cores against software-controlled hardware trojans
D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 27-32, 2019
62019
Platform independent 8-bit soft-core for SoPC
F Merchant, S Pujari, M Patil
Proceedings of the International MultiConference of Engineers and Computer†…, 2009
62009
Inter-lock: Logic encryption for processor cores beyond module boundaries
D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss
2019 IEEE European Test Symposium (ETS), 1-6, 2019
42019
ExPAN (N) D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
S Nambi, S Ullah, A Lohana, SS Sahoo, F Merchant, A Kumar
arXiv preprint arXiv:2010.12869, 2020
32020
A secure hardware-software solution based on RISC-V, logic locking and microkernel
D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ...
Proceedings of the 23th International Workshop on Software and Compilers for†…, 2020
32020
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