Automatic synthesis of systolic arrays from uniform recurrent equations P Quinton ACM SIGARCH Computer architecture news 12 (3), 208-214, 1984 | 496 | 1984 |

The systematic design of systolic arrays P Quinton INRIA, 1983 | 298* | 1983 |

The mapping of linear recurrence equations on regular arrays P Quinton, V Van Dongen Journal of VLSI signal processing systems for signal, image and video …, 1989 | 297 | 1989 |

Systolic algorithms & architectures P Quinton, Y Robert Prentice Hall, 1991 | 185 | 1991 |

Parallel algorithms and architectures M Cosnard, P Quinton, Y Robert, M Tchuente North Holland, 1986 | 184 | 1986 |

The ALPHA language and its use for the design of systolic arrays H Le Verge, C Mauras, P Quinton Journal of VLSI signal processing systems for signal, image and video …, 1991 | 134 | 1991 |

Algorithmes et architectures systoliques P Quinton, Y Robert Masson, 1989 | 113 | 1989 |

Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays V Van Dongen, P Quinton Proceedings. International Conference on Systolic Arrays, 473,474,475,476 …, 1988 | 111 | 1988 |

Synthesizing systolic arrays using DIASTOL P Gachet, B Joinnault, P Quinton International workshop on systolic arrays, 25-36, 1986 | 79 | 1986 |

Scheduling affine parameterized recurrences by means of C Mauras, P Quinton, S Rajopadhye, Y Saouter [1990] Proceedings of the International Conference on Application Specific …, 1990 | 70 | 1990 |

Computability of recurrence equations Y Saouter, P Quinton Theoretical Computer Science 116 (2), 317-337, 1993 | 62 | 1993 |

ompVerify: polyhedral analysis for the OpenMP programmer V Basupalli, T Yuki, S Rajopadhye, A Morvan, S Derrien, P Quinton, ... International Workshop on OpenMP, 37-53, 2011 | 58 | 2011 |

Systolic array processors JV McCanny, JG McWhirter, EE Swartzlander Jr Prentice Hall International, 1989 | 56* | 1989 |

Mapping recurrences on parallel architectures P Quinton Proc. of Int. Conf on Supercomputing ICS 88, 1-8, 1988 | 54 | 1988 |

Polyhedral bubble insertion: A method to improve nested loop pipelining for high-level synthesis A Morvan, S Derrien, P Quinton IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 45 | 2013 |

A Theorem-Prover for a Decidable Subset of Default Logic. P Besnard, R Quiniou, P Quinton AAAI 83, 27-30, 1983 | 45 | 1983 |

Extension of Chernikova's algorithm for solving general mixed linear programming problems F Fernandez, P Quinton INRIA, 1988 | 44 | 1988 |

Parallelizing HMMER for hardware acceleration on FPGAs S Derrien, P Quinton 2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007 | 38 | 2007 |

Hardware synthesis for multi-dimensional time AC Guillou, P Quinton, T Risset Proceedings IEEE International Conference on Application-Specific Systems …, 2003 | 36 | 2003 |

On manipulating Z-polyhedra using a canonical representation P Quinton, S Rajopadhye, T Risset Parallel Processing Letters 7 (02), 181-194, 1997 | 36 | 1997 |