| Pulser gating: A clock gating of pulsed-latch circuits S Kim, I Han, S Paik, Y Shin 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 190-195, 2011 | 31 | 2011 |
| Wakeup synthesis and its buffered tree construction for power gating circuit designs S Paik, S Kim, Y Shin Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 6 | 2010 |
| Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating C Oh, S Kim, Y Shin 2009 IEEE International Conference on IC Design and Technology, 59-62, 2009 | 5 | 2009 |
| Pulsed-latch aware placement for timing-integrity optimization YL Chuang, S Kim, Y Shin, YW Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 4 | 2011 |
| Wakeup scheduling and its buffered tree synthesis for power gating circuits S Kim, S Paik, S Kang, Y Shin Integration 53, 157-170, 2016 | 3 | 2016 |
| Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization S Kim, S Kang, Y Shin ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (3 …, 2016 | 2 | 2016 |
| Pulsed-latch ASIC synthesis in industrial design flow S Kim, D Kim, Y Shin 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 356-361, 2013 | | 2013 |
