| Pulsed-latch circuits: A new dimension in ASIC design Y Shin, S Paik IEEE Design & Test of Computers 28 (6), 50-57, 2011 | 36 | 2011 |
| Pulser gating: A clock gating of pulsed-latch circuits S Kim, I Han, S Paik, Y Shin 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 190-195, 2011 | 31 | 2011 |
| Pulse width allocation and clock skew scheduling: Optimizing sequential circuits based on pulsed latches H Lee, S Paik, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 23 | 2010 |
| Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits S Lee, S Paik, Y Shin Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 22 | 2009 |
| Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits H Lee, S Paik, Y Shin 2008 IEEE/ACM International Conference on Computer-Aided Design, 224-229, 2008 | 22 | 2008 |
| HLS-l: A High-Level Synthesis framework for latch-based architectures S Paik, I Shin, T Kim, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 21 | 2010 |
| Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power S Paik, GJ Nam, Y Shin Proceedings of the International Conference on Computer-Aided Design, 640-646, 2011 | 19 | 2011 |
| Register allocation for high-level synthesis using dual supply voltages I Shin, S Paik, Y Shin Proceedings of the 46th Annual Design Automation Conference, 937-942, 2009 | 19 | 2009 |
| Statistical time borrowing for pulsed-latch circuit designs S Paik, L Yu, Y Shin 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 675-680, 2010 | 17 | 2010 |
| Semicustom design of zigzag power-gated circuits in standard cell elements Y Shin, S Paik, HO Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 14 | 2009 |
| HLS-dv: A high-level synthesis framework for dual-Vdd architectures I Shin, S Paik, D Shin, Y Shin IEEE transactions on very large scale integration (VLSI) systems 20 (4), 593-604, 2011 | 13 | 2011 |
| Retiming pulsed-latch circuits with regulating pulse width S Paik, S Lee, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 11 | 2011 |
| Pulsed-latch circuits to push the envelope of ASIC design S Paik, Y Shin 2010 International SoC Design Conference, 150-153, 2010 | 10 | 2010 |
| Selectively patterned masks: Structured ASIC with asymptotically ASIC performance D Baek, I Shin, S Paik, Y Shin 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 376-381, 2011 | 8 | 2011 |
| Clock gating synthesis of pulsed-latch circuits S Paik, I Han, S Kim, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 6 | 2012 |
| Wakeup synthesis and its buffered tree construction for power gating circuit designs S Paik, S Kim, Y Shin Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 6 | 2010 |
| Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements S Paik, Y Shin Proceedings of the 45th annual Design Automation Conference, 600-605, 2008 | 4 | 2008 |
| Linear complexity prioritization of timing engineering change order failures N Oh, S Paik, J Wang US Patent 9,390,221, 2016 | 3 | 2016 |
| Wakeup scheduling and its buffered tree synthesis for power gating circuits S Kim, S Paik, S Kang, Y Shin Integration 53, 157-170, 2016 | 3 | 2016 |
| Exploring the opportunity of optimizing sequencing elements in ASIC designs S Paik, J Kung, Y Shin 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 1 | 2011 |
Youngsoo ShinProfessor of Electrical Engineering, KAISTVerified email at ee.kaist.ac.kr
