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Seungwhun Paik
Seungwhun Paik
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Title
Cited by
Cited by
Year
Pulsed-latch circuits: A new dimension in ASIC design
Y Shin, S Paik
IEEE Design & Test of Computers 28 (6), 50-57, 2011
352011
Pulser gating: A clock gating of pulsed-latch circuits
S Kim, I Han, S Paik, Y Shin
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 190-195, 2011
282011
Pulse width allocation and clock skew scheduling: Optimizing sequential circuits based on pulsed latches
H Lee, S Paik, Y Shin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
222010
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits
S Lee, S Paik, Y Shin
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
222009
HLS-l: A High-Level Synthesis framework for latch-based architectures
S Paik, I Shin, T Kim, Y Shin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
212010
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits
H Lee, S Paik, Y Shin
2008 IEEE/ACM International Conference on Computer-Aided Design, 224-229, 2008
212008
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
S Paik, GJ Nam, Y Shin
Proceedings of the International Conference on Computer-Aided Design, 640-646, 2011
192011
Register allocation for high-level synthesis using dual supply voltages
I Shin, S Paik, Y Shin
2009 46th ACM/IEEE Design Automation Conference, 937-942, 2009
182009
Statistical time borrowing for pulsed-latch circuit designs
S Paik, L Yu, Y Shin
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 675-680, 2010
162010
Semicustom design of zigzag power-gated circuits in standard cell elements
Y Shin, S Paik, HO Kim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
132009
HLS-dv: A high-level synthesis framework for dual-Vdd architectures
I Shin, S Paik, D Shin, Y Shin
IEEE transactions on very large scale integration (VLSI) systems 20 (4), 593-604, 2011
122011
Retiming pulsed-latch circuits with regulating pulse width
S Paik, S Lee, Y Shin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
102011
Pulsed-latch circuits to push the envelope of ASIC design
S Paik, Y Shin
2010 International SoC Design Conference, 150-153, 2010
92010
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance
D Baek, I Shin, S Paik, Y Shin
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 376-381, 2011
82011
Clock gating synthesis of pulsed-latch circuits
S Paik, I Han, S Kim, Y Shin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
62012
Wakeup synthesis and its buffered tree construction for power gating circuit designs
S Paik, S Kim, Y Shin
Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010
62010
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements
S Paik, Y Shin
2008 45th ACM/IEEE Design Automation Conference, 600-605, 2008
42008
Wakeup scheduling and its buffered tree synthesis for power gating circuits
S Kim, S Paik, S Kang, Y Shin
Integration 53, 157-170, 2016
32016
Linear complexity prioritization of timing engineering change order failures
N Oh, S Paik, J Wang
US Patent 9,390,221, 2016
22016
Exploring the opportunity of optimizing sequencing elements in ASIC designs
S Paik, J Kung, Y Shin
2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011
12011
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