| Timing verification using statically sensitizable paths J Benkoski, EV Meersch, LJM Claesen, H De Man IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990 | 146 | 1990 |
| Efficient algorithms for solving the false path problem in timing verifiers J Benkoski, EV Meersch, L Claesen, H De Man Digest of technical papers IC-CAD'87, 24-28, 1987 | 138* | 1987 |
| EFFICIENT ALGORITHMS FOR SOLVING THE FALSE PATH PROBLEM IN TIMING VERIFICATION. J Benkoski, E Vanden Meersch, L Claesen, H De Man | 132 | 1987 |
| A new approach to hierarchical and statistical timing simulations J Benkoski, AJ Strojwas IEEE transactions on computer-aided design of integrated circuits and …, 1987 | 46 | 1987 |
| Hard macros will revolutionize SoC design E Wein, J Benkoski EE Times, 2004 | 27 | 2004 |
| Applying a submicron mismatch model to practical IC design C Guardiani, A Tomasini, J Benkoski, M Quarantelli, P Gubian Proceedings of IEEE Custom Integrated Circuits Conference-CICC'94, 297-300, 1994 | 25 | 1994 |
| Yield optimization of analog ics using two-step analytic modeling methods C Guardiani, P Scandolara, J Benkoski, G Nicollini IEEE journal of solid-state circuits 28 (7), 778-783, 1993 | 19 | 1993 |
| The role of timing verification in layout synthesis J Benkoski, AJ Strojwas Proceedings of the 28th ACM/IEEE Design Automation Conference, 612-619, 1991 | 19 | 1991 |
| Static timing analysis using interval constraints R Stewart, J Benkoski 1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991 | 19 | 1991 |
| A practical approach to Top/Down analog circuit design JP Morin, F Lemery, E Nercessian, V Sharma, J Benkoski, D Samani ESSCIRC'93: Nineteenth European Solid-State Circuits Conference 1, 49-52, 1993 | 15 | 1993 |
| Timing verification by formal signal interaction modeling in a multi-level timing simulator J Benkoski, AJ Strojwas Proceedings of the 26th ACM/IEEE Design Automation Conference, 668-673, 1989 | 15 | 1989 |
| Statistical timing verification and delay fault detection by formal signal interaction modeling in a multi-level timing simulator. J Benkoski | 12 | 1990 |
| Simulation Algorithms, Power Estimation and Diagnostics in PowerMill J Benkoski, AC Deng, X Huang, S Napper, J Tuan PATMOS 95, 399-410, 1995 | 11* | 1995 |
| Computation of delay defect and delay fault probabilities using a statistical timing simulator J Benkoski, AJ Strojwas Proceedings.'Meeting the Tests of Time'., International Test Conference, 153-160, 1989 | 9 | 1989 |
| Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator J Besnard, J Benkoski, B Hennion Proceedings of the European Conference on Design Automation., 136-141, 1991 | 8 | 1991 |
| New techniques for statistical timing simulation J Benkoski, AJ Strojwas IEEE Int. Conf. Computer-Aided Des., Dig. Tech. Papers, 134-137, 1986 | 8 | 1986 |
| TATOO: an industrial timing analyzer with false path elimination and test pattern generation J Benkoski, RB Stewart Proceedings of the European Conference on Design Automation., 256-260, 1991 | 7 | 1991 |
| Behavioral models for complex top/down analog/digital system simulation F Lémery, JP Morin, E Nercessian, J Benkoski, D Samani Proceedings of the Conference on Modelling and Simulation, 1050-1054, 1994 | 4 | 1994 |
| Demosthenes-A technology-independent power DMOS layout generator G Fourneris, N Bekkara, J Benkoski, L Zullino, D Spatafora, G Martino Proceedings of EURO-DAC 93 and EURO-VHDL 93-European Design Automation …, 1993 | 4 | 1993 |
| Flow-driven graphical user interface for parametric and statistical design optimization C Guardiani, J Benkoski Proceedings of IEEE Custom Integrated Circuits Conference-CICC'93, 13.5. 1 …, 1993 | 3 | 1993 |
