Giorgos Dimitrakopoulos

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Chrysostomos NicopoulosAssociate Professor, Department of ECE, University of CyprusVerified email at ucy.ac.cy
Anastasios PsarrasSoC Design Engineer @ Axelera AIVerified email at ee.duth.gr
Dimitris NikolosProfessor, Computer Engineering & Informatics Dept, University of PatrasVerified email at ceid.upatras.gr
Ioannis SeitanidisSynopsysVerified email at synopsys.com
Haridimos T. VergosProfessor, Computer Engineering & Informatics Dept, University of PatrasVerified email at ceid.upatras.gr
Dionysios FilippasPh.D Student, Democritus University of ThraceVerified email at ee.duth.gr
Georgios Ch. SirakoulisProfessor, Democritus University of Thrace, GreeceVerified email at ee.duth.gr
Constantinos EfstathiouProfessor, Dept. of Informatics and Computer Engineering, University of West AtticaVerified email at uniwa.gr
Emmanouil KalligerosUniversity of the AegeanVerified email at aegean.gr
Christodoulos PeltekisPhD Student, Democritus University of ThraceVerified email at ee.duth.gr
Nikolaos ChrysosFoundation For Research & Technology (FORTH) -- HellasVerified email at ics.forth.gr
David ChinnerySiemens EDAVerified email at mentor.com
Junghee LeeAssistant Professor of School of Cyber Security, Korea UniversityVerified email at korea.ac.kr
Yiannakis (Yanos) SazeidesUniversity of CyprusVerified email at cs.ucy.ac.cy
Jose FlichAssociate Professor, Technical University of ValenciaVerified email at disca.upv.es
Vassilis PaliourasProfessor, Department of Electrical and Computer Engineering, University of PatrasVerified email at ece.upatras.gr
Iosif-Angelos FyrigosDemocritus University of ThraceVerified email at ee.duth.gr
Sorin CotofanaQuantum & Computer Engineering, Delft University of TechnologyVerified email at tudelft.nl
Dimitris NikolosVerified email at upatras.gr
Vasileios NtinasPostdoctoral Research Associate, Technische Universität DresdenVerified email at tu-dresden.de

Giorgos Dimitrakopoulos

Professor, ECE, Democritus University of Thrace

Verified email at ee.duth.gr - Homepage

VLSI Integrated Circuits Electronic Design Automation Computer Architecture Computer Arithmetic


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High-speed parallel-prefix VLSI Ling adders G Dimitrakopoulos, D Nikolos IEEE Transactions on Computers 54 (2), 225-231, 2005	213	2005
Efficient diminished-1 modulo 2/sup n/+ 1 multipliers C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos IEEE Transactions on Computers 54 (4), 491-496, 2005	97	2005
Microarchitecture of Network-on-chip Routers G Dimitrakopoulos, A Psarras, I Seitanidis Springer, 2015	83	2015
On modulo 2^ n+ 1 adder design HT Vergos, G Dimitrakopoulos IEEE transactions on computers 61 (2), 173-186, 2010	82	2010
Low-power leading-zero counting and anticipation logic for high-speed floating point units G Dimitrakopoulos, K Galanopoulos, C Mavrokefalidis, D Nikolos IEEE transactions on very large scale integration (VLSI) systems 16 (7), 837-850, 2008	69	2008
Fast arbiters for on-chip network switches G Dimitrakopoulos, N Chrysos, K Galanopoulos 2008 IEEE International Conference on Computer Design, 664-670, 2008	65	2008
The fast evolving landscape of on-chip communication: Selected future challenges and research avenues D Bertozzi, G Dimitrakopoulos, J Flich, S Sonntag Design Automation for Embedded Systems 19, 59-76, 2015	59	2015
ShortPath: A network-on-chip router with fine-grained pipeline bypassing A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computers 65 (10), 3136-3147, 2016	48	2016
New architectures for modulo 2n-1 adders G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou 2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005	48	2005
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015	42	2015
RISC-V²: A Scalable RISC-V Vector Processor K Patsidis, C Nicopoulos, GC Sirakoulis, G Dimitrakopoulos 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020	40	2020
ElastiStore: Flexible elastic buffering for virtual-channel-based networks on chip I Seitanidis, A Psarras, K Chrysanthou, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015	37	2015
Elastistore: An elastic buffer architecture for network-on-chip routers I Seitanidis, A Psarras, G Dimitrakopoulos, C Nicopoulos 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014	32	2014
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension K Patsidis, D Konstantinou, C Nicopoulos, G Dimitrakopoulos Microprocessors and Microsystems 61, 1-10, 2018	29	2018
PhaseNoC: Versatile network traffic isolation through TDM-scheduled virtual channels A Psarras, J Lee, I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015	29	2015
Merged switch allocation and traversal in network-on-chip switches G Dimitrakopoulos, E Kalligeros, K Galanopoulos IEEE Transactions on Computers 62 (10), 2001-2012, 2012	28	2012
A low-power network-on-chip architecture for tile-based chip multi-processors A Psarras, J Lee, P Mattheakis, C Nicopoulos, G Dimitrakopoulos Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 335-340, 2016	23	2016
LP-NUCA: Networks-in-cache for high-performance low-power embedded processors DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011	23	2011
Networks-on-chip with double-data-rate links A Psarras, S Moisidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Circuits and Systems I: Regular Papers 64 (12), 3103-3114, 2017	22	2017
ElastiNoC: A self-testable distributed VC-based network-on-chip architecture I Seitanidis, A Psarras, E Kalligeros, C Nicopoulos, G Dimitrakopoulos 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 135-142, 2014	22	2014

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