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| Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor J Sankaranarayanan, DK Mandal US Patent App. 14/931,322, 2016 | 8 | 2016 |
| Optimized fast feature detection for vector processors J Sankaranarayanan, DK Mandal, PR Viswanath US Patent 9,652,686, 2017 | 5 | 2017 |
| Optimized Fast Feature Detection for Vector Processors J Sankaranarayanan, DK Mandal, PR Viswanath US Patent App. 14/581,401, 2016 | 3 | 2016 |
| Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor J Sankaranarayanan, DK Mandal US Patent App. 16/552,387, 2020 | 1 | 2020 |
| Method for performing random read access to a block of data using parallel lut read instruction in vector processors J Sankaranarayanan, DK Mandal US Patent App. 18/321,037, 2023 | | 2023 |
| Method for performing random read access to a block of data using parallel LUT read instruction in vector processors J Sankaranarayanan, DK Mandal US Patent 11,669,330, 2023 | | 2023 |
| Method for performing random read access to a block of data using parallel LUT read instruction in vector processors J Sankaranarayanan, DK Mandal US Patent 10,996,955, 2021 | | 2021 |
| Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor J Sankaranarayanan, DK Mandal US Patent 10,395,381, 2019 | | 2019 |
| Method for performing random read access to a block of data using parallel LUT read instruction in vector processors J Sankaranarayanan, DK Mandal US Patent 10,331,347, 2019 | | 2019 |
