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Dipan Mandal
Dipan Mandal
Senior Principal Architect, ARM
Verified email at arm.com - Homepage
Title
Cited by
Cited by
Year
Method for performing random read access to a block of data using parallel lut read instruction in vector processors
J Sankaranarayanan, DK Mandal
US Patent App. 14/920,365, 2016
262016
Embedding stall and event trace profiling data in the timing stream-extended timing trace circuits, processes, and systems
KG Bansal, DK Mandal, GA Cooper, BJ Thome
US Patent App. 13/396,001, 2012
242012
An Embedded Vision Engine (EVE) for automotive vision processing
DK Mandal, J Sankaran, A Gupta, K Castille, S Gondkar, S Kamath, ...
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 49-52, 2014
182014
High throughput VLSI architecture for HEVC SAO encoding for ultra HDTV
M Mody, H Garud, S Nagori, DK Mandal
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2620-2623, 2014
172014
Optimized image feature extraction
GS Kalsi, OJ Omer, B George, G Neela, DK Mandal, S Subramoney
US Patent App. 10/318,834, 2019
15*2019
Optical flow determination using pyramidal block matching
HT Garud, SN Nagori, DK Mandal
US Patent 9,681,150, 2017
142017
Optical flow determination using pyramidal block matching
HT Garud, SN Nagori, DK Mandal
US Patent 9,681,150, 2017
142017
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power
DK Mandal, S Jandhyala, OJ Omer, GS Kalsi, B George, G Neela, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 960-963, 2019
112019
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator
NK Jha, S Ravishankar, S Mittal, A Kaushik, D Mandal, M Chandra
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 574-579, 2020
92020
Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment
D Mandal, B Thome
US Patent App. 11/413,406, 2007
92007
Scalable memory-optimized hardware for matrix-solve
GS Kalsi, OJ Omer, DK Mandal, SK Rethinagiri, G Neela
US Patent App. 10/324,689, 2019
8*2019
Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor
J Sankaranarayanan, DK Mandal
US Patent App. 14/931,322, 2016
72016
A 28nm programmable and low power ultra-HD video codec engine
H Sanghvi, M Mody, N Nandan, M Mehendale, S Das, DK Mandal, ...
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 558-561, 2014
62014
Technologies for feature detection and tracking
DK Mandal, OJ Omer, LE Hacking, J Radford, S Subramoney, E Jones, ...
US Patent App. 15/826,524, 2018
52018
Prioritizing stall/reason data into priority information stream over PC/data trace
KG Bansal, DK Mandal, GA Cooper, BJ Thome
US Patent 8,943,369, 2015
5*2015
Accelerator for matrix decomposition
GS Kalsi, OJ Omer, SK Rethinagiri, NK Anish, DK Mandal
US Patent 10,540,420, 2020
42020
Scalable memory-optimized hardware for matrix-solve
GS Kalsi, OJ Omer, DK Mandal, SK Rethinagiri, G Neela
US Patent 10,324,689, 2019
42019
Data system simulated event and matrix debug of pipelined processor
DK Mandal, BJ Thome
US Patent 7,685,467, 2010
42010
Towards Noise Resilient SLAM
A Thyagharajan, OJ Omer, D Mandal, S Subramoney
2020 IEEE International Conference on Robotics and Automation (ICRA), 72-79, 2020
32020
Optimized fast feature detection for vector processors
J Sankaranarayanan, DK Mandal, PR Viswanath
US Patent 9,652,686, 2017
32017
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