| Redefine: Runtime reconfigurable polymorphic asic M Alle, K Varadarajan, A Fell, N Joseph, S Das, P Biswas, J Chetia, A Rao, ... ACM Transactions on Embedded Computing Systems (TECS) 9 (2), 1-48, 2009 | 64 | 2009 |
| Compiling HPC kernels for the REDEFINE CGRA KT Madhu, S Das, S Nalesh, SK Nandy, R Narayan 2015 IEEE 17th International Conference on High Performance Computing and …, 2015 | 21 | 2015 |
| A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ... Journal of Systems Architecture 60 (7), 592-614, 2014 | 21 | 2014 |
| A systolic dataflow based accelerator for CNNs S Das, A Roy, KK Chandrasekharan, A Deshwal, S Lee 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 14 | 2020 |
| Streaming FFT on REDEFINE-v2: An application-architecture design space exploration A Fell, M Alle, K Varadarajan, P Biswas, S Das, J Chetia, SK Nandy, ... Proceedings of the 2009 international conference on Compilers, architecture …, 2009 | 13 | 2009 |
| Rhyme: Redefine hyper cell multicore for accelerating hpc kernels S Das, N Sivanandan, KT Madhu, SK Nandy, R Narayan 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 11 | 2016 |
| Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath KT Madhu, S Das, SK Nandy, R Narayan Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS …, 2014 | 11 | 2014 |
| Energy aware synthesis of application kernels expressed in functional languages on a coarse grained composable reconfigurable array S Nalesh, KT Madhu, S Das, SK Nandy, R Narayan 2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015 | 4 | 2015 |
| A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture. G Garga, S Das, SK Nandy, R Narayan, C Haldar, MP Jagtap, SP Dash Defence Science Journal 62 (1), 2012 | 3 | 2012 |
| Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture R Krishnamoorthy, S Das, K Varadarajan, M Alle, M Fujita, R Narayan IPSJ Transactions on System and LSI Design Methodology 4, 193-209, 2011 | 3 | 2011 |
| Method and apparatus for processing computation of zero value in processing of layers in neural network S Das, S Kusuma, SH Lee, A Deshwal, KK Chandrasekharan US Patent 11,604,958, 2023 | 2 | 2023 |
| Energy aware synthesis of application kernels through composition of data-paths on a CGRA S Nalesh, KT Madhu, S Das, SK Nandy, R Narayan Integration 58, 320-328, 2017 | 2 | 2017 |
| A method for flexible reduction over binary fields using a field multiplier S Das, K Varadarajan, G Garga, R Mondal, R Narayan, SK Nandy Proceedings of the International Conference on Security and Cryptography, 50-58, 2011 | 2 | 2011 |
| Electronic device and method for inference binary and ternary neural networks A Roy, S Das, A Deshwal, KKC HARAN, SH Lee US Patent App. 17/098,589, 2021 | 1 | 2021 |
| Flexible resource allocation and management for application graphs on renE mpsoc KT Madhu, A Rao, S Das, KC Madhava, SK Nandy, R Narayan Proceedings of the 7th Workshop on Parallel Programming and Run-Time …, 2016 | 1 | 2016 |
| Method and apparatus for processing computation of zero value in processing of layers in neural network S Das, S Kusuma, SH Lee, A Deshwal, KK Chandrasekharan US Patent 11,915,118, 2024 | | 2024 |
| Method and system of performing convolution in neural networks with variable dilation rate DK Yadav, A Deshwal, S Das, J Junwoo, SH Lee US Patent 11,854,174, 2023 | | 2023 |
| Method and system of performing convolution in neural networks with variable dilation rate DK Yadav, A Deshwal, S Das, J Junwoo, SH Lee US Patent 11,423,251, 2022 | | 2022 |
| Apparatus with accelerated machine learning processing S Das, S Kusuma, A Roy, A Deshwal, KK Chandrasekharan, SH Lee US Patent App. 17/147,858, 2022 | | 2022 |
| Reconfigurable Accelerator for High Performance Application Kernels S Das | | 2021 |
Kavitha MadhuIndian Institute of Science, Argonne National Lab, Intel LabsVerified email at iisc.ac.in
