| Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s G Kim, JW Park, IG Kim, S Kim, S Kim, JM Lee, GS Park, J Joo, KS Jang, ... Optics Express 19 (27), 26936-26947, 2011 | 89 | 2011 |
| 29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration S Kim, HG Ko, SY Cho, J Lee, S Shin, MS Choo, H Chi, DK Jeong 2017 IEEE International Solid-State Circuits Conference (ISSCC), 494-495, 2017 | 33 | 2017 |
| 23.2 a 1.1 V 1ynm 6.4 Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, high-speed SerDes and RX/TX equalization scheme D Kim, M Park, S Jang, JY Song, H Chi, G Choi, S Choi, J Kim, C Kim, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 380-382, 2019 | 28 | 2019 |
| Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~ 1550 nm J Joo, KS Jang, SH Kim, IG Kim, JH Oh, SA Kim, GS Jeong, Y Kim, ... Optics express 23 (9), 12232-12243, 2015 | 26 | 2015 |
| A 40-Gb/s transceiver in 0.13-μm CMOS technology JK Kim, J Kim, G Kim, H Chi, DK Jeong 2008 IEEE Symposium on VLSI Circuits, 196-197, 2008 | 23 | 2008 |
| A 1.1-V 10-nm class 6.4-Gb/s/pin 16-Gb DDR5 SDRAM with a phase rotator-ILO DLL, high-speed SerDes, and DFE/FFE equalization scheme for Rx/Tx D Kim, M Park, S Jang, JY Song, H Chi, G Choi, S Choi, C Kim, M Han, ... IEEE Journal of Solid-State Circuits 55 (1), 167-177, 2019 | 22 | 2019 |
| Design of silicon photonic interconnect ICs in 65-nm CMOS technology W Bae, GS Jeong, Y Kim, HK Chi, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015 | 20 | 2015 |
| 12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS DW Kim, HK Chi, YS Chun, MH Chin, G Kim, DK Jeong 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1115-1118, 2013 | 14 | 2013 |
| A 20-Gb/s 1.27 pJ/b low-power optical receiver front-end in 65nm CMOS GS Jeong, H Chi, K Kim, DK Jeong 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1492-1495, 2014 | 13 | 2014 |
| A PVT-compensated 2.2 to 3.0 GHz digitally controlled oscillator for all-digital PLL A Kavala, W Bae, S Kim, GM Hong, H Chi, S Kim, DK Jeong JSTS: Journal of Semiconductor Technology and Science 14 (4), 484-494, 2014 | 12 | 2014 |
| A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier KS Park, BJ Yoo, MS Hwang, H Chi, HC Kim, JW Park, K Kim, DK Jeong 2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010 | 12 | 2010 |
| Semiconductor device GH Choi, HK Chi, M su Park US Patent 10,573,361, 2020 | 7 | 2020 |
| 0.11-2.5 GHz all-digital DLL for mobile memory interface with phase sampling window adaptation to reduce jitter accumulation JH Chae, M Kim, GM Hong, J Park, H Ko, WY Shin, H Chi, DK Jeong, ... JSTS: Journal of Semiconductor Technology and Science 17 (3), 411-424, 2017 | 7 | 2017 |
| A 1.74 mW/GHz 0.11–2.5 GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers JH Chae, GM Hong, J Park, M Kim, H Ko, WY Shin, H Chi, DK Jeong, ... 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 7 | 2015 |
| A PVT variation-robust all-digital injection-locked clock multiplier with real-time offset tracking using time-division dual calibration MS Choo, S Kim, HG Ko, SY Cho, K Park, J Lee, S Shin, H Chi, DK Jeong IEEE Journal of Solid-State Circuits 56 (8), 2525-2538, 2021 | 6 | 2021 |
| Injection-locked oscillator and semiconductor device including the same KIM Sungwoo, S Cho, CHI Hankyu, S Kim, DK Jeong US Patent 10,284,211, 2019 | 6 | 2019 |
| Clock generation circuit, interface circuit and semiconductor system using the same KH Kim, MJ Park, WY Shin, SE Lee, HK Chi, JW Han US Patent App. 15/190,495, 2017 | 5 | 2017 |
| A 500 MHz-to-1.2 GHz reset free delay locked loop for memory controller with hysteresis coarse lock detector HK Chi, MS Hwang, BJ Yoo, WJ Choe, TH Kim, YS Moon, DK Jeong JSTS: Journal of Semiconductor Technology and Science 11 (2), 73-79, 2011 | 4 | 2011 |
| A clock synchronization system with IEEE 1588–2008 adapters over existing gigabit Ethernet equipment J Han, H Chi, DK Jeong Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 4 | 2010 |
| Receiver, system including the same, and calibration method thereof HK Chi, TS Song, YE Seok-Min, H Gi-Moon, BAE Woo-Rham, ... US Patent 9,059,825, 2015 | 3 | 2015 |
