Rubén Gran Tejero
Rubén Gran Tejero
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Cited by
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL
MA Dávila Guzmán, R Nozal, R Gran Tejero, M Villarroya-Gaudó, ...
The Journal of Supercomputing 75, 1732-1746, 2019
Adaptive partitioning for irregular applications on heterogeneous CPU-GPU chips
A Vilches, R Asenjo, A Navarro, F Corbera, R Gran, M Garzarán
Procedia Computer Science 51, 140-149, 2015
Mapping streaming applications on commodity multi-CPU and GPU on-chip processors
A Vilches, A Navarro, R Asenjo, F Corbera, R Gran, MJ Garzarán
IEEE Transactions on Parallel and Distributed Systems 27 (4), 1099-1115, 2015
Simultaneous multiprocessing in a software-defined heterogeneous FPGA
J Nunez-Yanez, S Amiri, M Hosseinabady, A Rodríguez, R Asenjo, ...
The Journal of Supercomputing 75, 4078-4095, 2019
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs
A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ...
Journal of Systems Architecture 98, 27-40, 2019
Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform
A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ...
The Journal of Supercomputing 76, 4645-4665, 2020
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache
J Albericio, R Gran, P Ibánez, V Viñals, JM Llabería
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012
Directive-based compilers for GPUs
S Ghike, R Gran, MJ Garzarán, D Padua
Languages and Compilers for Parallel Computing: 27th International Workshop …, 2015
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis
MA Dávila-Guzmán, R Gran Tejero, M Villarroya-Gaudó, DS Gracia
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
Hardware architectural support for caching partitioned reconfigurations in reconfigurable systems
JA Clemente, R Gran, A Chocano, C del Prado, J Resano
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 530-543, 2015
ACDC: small, predictable and high-performance data cache
J Segarra, C Rodriguez, R Gran, LC Aparicio, V Vinals
ACM Transactions on Embedded Computing Systems (TECS) 14 (2), 1-26, 2015
An Enhancement for a Scheduling Logic Pipelined over two Cycles
R Gran, E Morancho, À Olivé, JM Llaberia
2006 International Conference on Computer Design, 203-209, 2006
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators
N Landeros Muñoz, A Valero, R Gran Tejero, D Zoni
Journal of Systems Architecture, 102553, 2022
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
A Rodríguez, A Navarro, K Nikov, J Nunez-Yanez, R Gran, DS Gracia, ...
Journal of Systems Architecture 124, 102398, 2022
A Cross-Platform OpenVX Library for FPGA Accelerators
MA Dávila-Guzmán, R Gran Tejero, M Villarroya-Gaudó, DS Gracia, ...
2021 29th Euromicro International Conference on Parallel, Distributed and …, 2021
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches
J Segarra, J Cortadella, R Gran Tejero, V Viñals-Yúfera
IEEE access 8, 192379-192392, 2020
Reducing the WCET and analysis time of systems with simple lockable instruction caches
A Pedro-Zapater, J Segarra, R Gran Tejero, V Viñals, C Rodríguez
PLoS One 15 (3), e0229980, 2020
A predictable hardware to exploit temporal reuse in real-time and embedded systems
R Gran, J Segarra, A Pedro-Zapater, LC Aparicio, V Viñals, C Rodríguez
Journal of Systems Architecture 61 (5-6), 227-238, 2015
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
R Gran, J Segarra, C Rodríguez, LC Aparicio, V Viñals
Journal of Systems Architecture 59 (9), 667-678, 2013
First Steps Towards CPU, GPU, and FPGA Parallel Execution with EngineCL
MA Dávila-Guzmán, R Nozal, R Gran, M Villaroya-Gaudó, D Suárez, ...
Proc. 18th Int. Conf. Comput. Math. Method Sci. Eng. C, 2018
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