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Muhammad Shoaib Bin Altaf
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The gem5 simulator
N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ...
ACM SIGARCH computer architecture news 39 (2), 1-7, 2011
60902011
Modular routing design for chiplet-based systems
J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
1242018
The Gem5 Simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1–7
N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ...
772011
Logca: A high-level performance model for hardware accelerators
MSB Altaf, DA Wood
ACM SIGARCH Computer Architecture News 45 (2), 375-388, 2017
532017
A high accuracy and low latency patient-specific wearable fall detection system
W Saadeh, MAB Altaf, MSB Altaf
2017 IEEE EMBS International Conference on Biomedical & Health Informatics …, 2017
332017
LogCA: A Performance Model for Hardware Accelerators
M Shoaib Bin Altaf, DA Wood
IEEE, 2014
22*2014
Prioritizing local and remote memory access in a non-uniform memory access architecture
MW Boyer, O Kayiran, Y Eckert, S Raasch, MSBIN ALTAF
US Patent 10,838,864, 2020
202020
Modular Routing Design for Chiplet-Based Systems. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 726–738
J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh
82018
Setting operating points for circuits in an integrated circuit chip
W Huang, Y Eckert, X An, MSB Altaf, J Yin
US Patent 10,097,091, 2018
22018
Setting operating points for circuits in an integrated circuit chip
W Huang, Y Eckert, X An, MSB Altaf, J Yin
US Patent 10,389,251, 2019
2019
Exploiting simple analytical models for modeling hardware accelerators
MSB Altaf
The University of Wisconsin-Madison, 2016
2016
A Parallel Viterbi Decoder Implementation for High Throughput
M Shoaib Bin Altaf
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Articles 1–12