EEE 421 VLSI Circuits


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1 EEE 421
2 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in k range) large fanout (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current No direct path steadystate between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
3 Transforming PMOS IV Lines Want common coordinate set V in, V out, and I Dn I DSp = I DSn V GSn = V in ; V GSp = V in  V DSn = V out ; V DSp = V out  I Dn Vout V in = V in = 1.5 V in = V in = 1.5 V GSp = 1 V GSp = 2.5 Mirror around xaxis V in = + V GSp I Dn = I Dp Horiz. shift over V out = + V DSp
4 CMOS Inverter Load Lines PMOS 2.5 X 14 NMOS V in = V V in = 2.5V 2 V in =.5V 1.5 V in = 2.V V in = 1.V V in = 2V.5 V in = 1.5V V in = 2.V V in = 2.5V 1 V in = 1.5V V out (V) V in = 1V V in = 1.5V V in =.5V V in = 1.V V in =.5V V in = V.25um, W/L n = 1.5, W/L p = 4.5, = 2.5V, V Tn =.4V, V Tp = .4V
5 CMOS Inverter VTC V out (V) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in (V)
6 Operating Regions Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B C D E V tn /2 +V tp V in
7 Beta Ratio If b p / b n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent V inverter DD V out p.1 n p 1 n V in
8 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range
9 Logic Levels To maximize noise margins, select logic levels at» unity gain point of DC transfer characteristic V out Unity Gain Points Slope = 1 V OH b p /b n > 1 V in V out V OL V tn V IL V IH  V tp V in
10 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes» Requires solving differential equations Input is usually considered to be a step or ramp» From to or vice versa
11 Inverter Step Response Ex: find step response of inverter driving load cap V ( t) u( t t ) V I V in out dv ( t t ) out dt ( t) V I DD dsn C DD ( t) load 2 dsn( t) 2 VDD V Vout VDD Vt Vout ( t) VDD V t V ( t) V V 2 D V out out D t t t V in (t) t I dsn (t) V in (t) V out (t) V out (t) C load t
12 Delay Definitions t pdr : rising propagation delay» Max time from input to rising output crossing /2 t pdf : falling propagation delay» Max time from input to falling output crossing /2 t pd : average propagation delay» t pd = (t pdr + t pdf )/2 t r : rise time» From output crossing.2 to.8 t f : fall time» From output crossing.8 to.2
13 Delay Definitions t cdr : rising contamination delay» Minimum time from input to rising output crossing /2 t cdf : falling contamination delay» Minimum time from input to falling output crossing /2 t cd : average contamination delay» t pd = (t cdr + t cdf )/2
14 Simulated Inverter Delay Solving differential equations by hand too hard SPICE simulator solves equations numerically» Uses more accurate IV models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps.5 V out.. 2p 4p 6p 8p 1n t(s)
15 Switching Waveforms Example: = 1. V, C L = 15 ff, f = 1 GHz
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